Abstract

This letter presents an output capacitor-less low-dropout regulator (LDO) topology that can operate from 0.58-to-0.9-V supply, and has a minimum dropout voltage of 50 mV. Compared with traditional analog LDOs, the proposed design incorporates a current reference into the regulator loop and uses current feedback to alleviate the design constraints caused by the limited voltage headroom. The LDO is implemented in a 0.13- $\mu \text{m}$ standard-threshold-voltage CMOS process. Measurement results show that depending on the supply voltage the quiescent power consumption is from 2.4 to 3.6 $\mu \text{W}$ , and the current efficiency is 99.8%. The mean value of the output voltage of 16 samples is 0.53 V and the standard deviation is around 4 mV. The load current range of the proposed LDO is from 0 to 3 mA, and it is capable of driving a load capacitor of up to 120 pF.

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