A Sub-1-V 100-mA OCL-LDO Regulator With Process-Temperature-Aware Design for Transient Sustainability

Abstract

In this article, an output-capacitorless low-dropout (OCL-LDO) regulator that features low-power, small-transient-spike, and process-temperature (PT)-aware design for transient sustainability is presented. The circuit architecture is based on the improved PT-aware current source for keeping stable bandwidth and the proposed PT-aware transistor biasing network in conjunction of dual fast local feedback (DFLF) loops in a single power transistor stage to yield both enhanced and sustained transient metrics under a sub-1-V supply. Fabricated in 40-nm CMOS technology, the regulator can deliver a full-load current of 100 mA at a 100-pF load under a 0.75-V supply. From the measured results of 12 samples, it consumes an average quiescent power of 19.5 $\mu \text{W}$ and quiescent current of 26 $\mu \text{A}$ . It displays an average settling time of 414 ns for a full-load current of 100 mA at room temperature. The average load transient voltage spike is 23.9 mV and small when compared to the reported works at a similar level of load current. Finally, the process corner simulations at different temperatures together with the 12 measured samples at temperature corners have validated the sustainability of transient metrics.