Output-capacitorless Low-dropout Regulator Research Articles

Transient Response Enhancement on the Output-Capacitorless Low-Dropout Regulator Using the Multipath Nested Miller Compensation with a Transient Quiescent Current Booster

Transient Response Enhancement on the Output-Capacitorless Low-Dropout Regulator Using the Multipath Nested Miller Compensation with a Transient Quiescent Current Booster

A 6-$\mu$W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

An output-capacitorless low-dropout regulator (LDO) compensated by a single Miller capacitor is implemented in a commercial 90-nm CMOS technology. The proposed LDO makes use of the small transistors realized in nano-scale technology to achieve high stability, fast transient performance and small voltage spikes under rapid load-current changes without the need of an off-chip capacitor connected at the LDO output. Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF (estimated equivalent parasitic capacitance from load circuits) and with load capability of 100 mA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the embedded power transistor promptly. The measured power consumption is only 6 μW under a 0.75-V supply. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 μs.

An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection

An output-capacitorless low-dropout regulator (LDO) with a direct voltage-spike detection circuit is presented in this paper. The proposed voltage-spike detection is based on capacitive coupling. The detection circuit makes use of the rapid transient voltage at the LDO output to increase the bias current momentarily. Hence, the transient response of the LDO is significantly enhanced due to the improvement of the slew rate at the gate of the power transistor. The proposed voltage-spike detection circuit is applied to an output-capacitorless LDO implemented in a standard 0.35-?m CMOS technology (where VTHN ? 0.5 V and VTHP ? -0.65 V). Experimental results show that the LDO consumes 19 ?A only. It regulates the output at 0.8 V from a 1-V supply, with dropout voltage of 200 mV at the maximum output current of 66.7 mA. The voltage spike and the recovery time of the LDO with the proposed voltage-spike detection circuit are reduced to about 70 mV and 3 ?s, respectively, whereas they are more than 420 mV and 30 ?s for the LDO without the proposed detection circuit.