Optimized Hardware Architecture Research Articles

Multilayer Neural Network Hardware Designs for Faster Convolutional Processing

The demand for efficient hardware implementations of convolutional neural networks (CNNs) has surged with the proliferation of deep learning applications in various domains such as computer vision, natural language processing, and autonomous systems. Convolutional layers, being the fundamental building blocks of CNNs, are computationally intensive, requiring optimized hardware architectures for real-time inference tasks. This paper presents novel hardware designs targeting faster convolutional processing within multilayer neural networks. We propose a multi-faceted approach that leverages parallelism, pipelining, and hardware acceleration techniques to enhance the efficiency of convolution operations. Our design optimally exploits the inherent data-level and model-level parallelism present in CNNs to achieve high throughput while minimizing latency.

A Hardware-Efficient Perturbation Method to the Digital Tent Map

Digital chaotic systems used in various applications such as signal processing, artificial intelligence, and communications often suffer from the issue of dynamical degradation. This paper proposes a solution to address this problem in the digital tent map. Our proposed method includes a simple and optimized hardware architecture, along with a hardware-efficient perturbation method, to create a high-performance computing system that retains its chaotic properties. We implemented our proposed architecture using an FPGA (Field-Programmable Gate Array) and the 1’s complement fixed-point format. Our results demonstrate that the implemented digital circuit reduces logical resource consumption compared to state-of-the-art references and exhibits pseudo-random nature, as confirmed by various statistical tests. We validated our proposed pseudo-random number generator in a hardware architecture for particle swarm optimization, demonstrating its effectiveness.

Uniformity Correction of CMOS Image Sensor Modules for Machine Vision Cameras.

Flat-field correction (FFC) is commonly used in image signal processing (ISP) to improve the uniformity of image sensor pixels. Image sensor nonuniformity and lens system characteristics have been known to be temperature-dependent. Some machine vision applications, such as visual odometry and single-pixel airborne object tracking, are extremely sensitive to pixel-to-pixel sensitivity variations. Numerous cameras, especially in the fields of infrared imaging and staring cameras, use multiple calibration images to correct for nonuniformities. This paper characterizes the temperature and analog gain dependence of the dark signal nonuniformity (DSNU) and photoresponse nonuniformity (PRNU) of two contemporary global shutter CMOS image sensors for machine vision applications. An optimized hardware architecture is proposed to compensate for nonuniformities, with optional parametric lens shading correction (LSC). Three different performance configurations are outlined for different application areas, costs, and power requirements. For most commercial applications, the correction of LSC suffices. For both DSNU and PRNU, compensation with one or multiple calibration images, captured at different gain and temperature settings are considered. For more demanding applications, the effectiveness, external memory bandwidth, power consumption, implementation, and calibration complexity, as well as the camera manufacturability of different nonuniformity correction approaches were compared.

Lite-Stereo: A Resource-Efficient Hardware Accelerator for Real-Time High-Quality Stereo Estimation Using Binary Neural Network

Stereo estimation plays a key role in many autonomous systems, such as robotics and self-driving cars. Recent work on StereoEngine, an FPGA-based accelerator for deep neural network (DNN)-based stereo estimation, has been demonstrated as a promising solution to achieve both real-time and high accuracy performance for depth sensing. However, this solution still suffers from over-utilizing the hardware resource of FPGAs. In this article, we present Lite-Stereo, a resource-efficient DNN-based stereo vision accelerator to improve the hardware efficiency for StereoEngine running on a resource-constrained FPGA. To achieve this, we design a set of optimized hardware architectures for resource-demanding bottleneck modules. In order to balance the gap between the processing speed and resource efficiency, the process elements in binary neural network modules are shared within and across modules. In addition, we provide reusing strategies on path aggregation and neighbor calculation to improve the resource efficiency of the semi-global matching module. Evaluation results demonstrate that Lite-Stereo reduces the hardware cost of ALUTs and RAM bits by 60% and 29%, respectively, without compromising the accuracy and energy efficiency compared with StereoEngine.

FPGA realization of fractals based on a new generalized complex logistic map

This paper introduces a new generalized complex logistic map and the FPGA realization of a corresponding fractal generation application. The chaotic properties of the proposed map are studied through the stability conditions, bifurcation behavior and maximum Lyapunov exponent (MLE). A relation between the mathematical analysis and fractal behavior is demonstrated, which enables formulating the fractal limits. A compact fractal generation process is presented, which results in designing and implementing an optimized hardware architecture. An efficient FPGA implementation of the fractal behavior is validated experimentally on Artix-7 FPGA board. Two examples of fractal implementation are verified, yielding frequencies of 34.593MHz and 31.979MHz and throughputs of 0.415 Gbit/s, 0.384 Gbit/s. Compared to recent related works, the proposed implementation demonstrates its efficient hardware utilization and suitability for potential applications.

High-throughput configurable SIMON architecture for flexible security

As the Internet of Things applications become mission-critical and their data more valuable, it becomes more and more essential to paramount their security. The security can be improved by using emerging light-weight ciphers. SIMON is a relatively recent family of light-weight ciphers which is proposed by the National Security Agency optimized for hardware platforms. In this paper, we propose an optimized hardware architecture for SIMON for high-throughput resource-constrained applications with multiple levels of security. Moreover, a configurable architecture with different operating modes is introduced for utilizing in applications requiring higher resistance to fault and power attacks. This architecture also supports an ultra-high-throughput mode for different key sizes. Implementation results of the proposed architectures on both ASIC and FPGA are reported. The comparison results show that our proposals outperform similar architectures in terms of some design metrics, e.g. throughput, which make it suitable for IoT applications. Finally, we implement practically our architecture on the Digilent-ZYBO board and report the experimental results.

An Optimized Architecture for Binary Huff Curves With Improved Security

In order to compute the elliptic curve point addition and doubling, the unified point addition law provides better protection against side channel attacks. One of the elliptic curve models, providing the unified point addition, is Binary Huff Curves (BHC). Recently, a new unified method for BHC with improved security against side channel attacks, has been proposed. Therefore, an optimized hardware architecture in terms of higher clock frequency and throughput for the new unified point addition method is required. Consequently, this article has three major contributions: The first contribution is to modify the unified addition law from hardware implementation point of view, resulting 31% decrease in memory requirements. The second contribution is the analysis of memory optimized unified law in the context of pipelining. In this regard, this article proposes an instruction scheduling policy for a 2-stage pipelined architecture which provides 36% reduction in the number of required clock cycles, 14.3% improvement in clock frequency, 53.2% decrease in computation time and 54.5% improvement in throughput/area. Finally, the third contribution is to propose a 4-stage pipelined architecture. The proposed 4-stage pipelined architecture provides an additional 19% improvement in clock frequency and 10% increase in throughput, as compared to the 2-stage pipelined architecture.

FPGA Acceleration for Big Data Analytics: Challenges and Opportunities

The big data revolution has ushered an era with ever increasing volumes and complexity of data requiring ever faster computational analysis. During this very same era, CPU performance growth has been stagnating, pushing the industry to either scale their computation horizontally using multiple nodes in datacenters, or to scale vertically using heterogeneous components to reduce compute time. However, networking and storage continue to provide both higher throughput and lower latency, which allows for leveraging heterogeneous components, deployed in data centers around the world. Still, the integration of big data analytics frameworks with heterogeneous hardware components such as GPGPUs and FPGAs is challenging, because there is an increasing gap in the level of abstraction between analytics solutions developed with big data analytics frameworks, and accelerated kernels developed with heterogeneous components. In this article, we focus on FPGA accelerators that have seen wide-scale deployment in large cloud infrastructures. FPGAs allow the implementation of highly optimized hardware architectures, tailored exactly to an application, and unburdened by the overhead associated with traditional general-purpose computer architectures. FPGAs implementing dataflow-oriented architectures with high levels of (pipeline) parallelism can provide high application throughput, often providing high energy efficiency. Latency-sensitive applications can leverage FPGA accelerators by directly connecting to the physical layer of a network, and perform data transformations without going through the software stacks of the host system. While these advantages of FPGA accelerators hold promise, difficulties associated with programming and integration limit their use. This article explores the existing practices in big data analytics frameworks, discusses the aforementioned gap in development abstractions, and provides some perspectives on how to address these challenges in the future.

Analysis and FPGA of semi-fractal shapes based on complex Gaussian map

Abstract This paper studies the fractal-like behavior exhibited by the complex form of Gaussian chaotic map and the capability of digital architectures to mimic that behavior. Digitally realized chaotic attractors had many applications; hopefully, a digital realization of fractals may achieve the same eventually. The Gauss map is viewed concerning its bifurcation behavior, time waveform plots, Lyapunov exponent, and attractor performance through parameter variation. The Fractal-like entities emerging from the perceived complex map are examined versus different map coefficients for the highest chaotic periods to extract an interpretation for the fractal behavior. FPGA implementation of the fractal behavior is discussed viewing an optimized hardware architecture that eventually displays a fractal entity experimentally.

An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment

This paper presents an optimized hardware architecture of the inverse quantization and the inverse transform (IQ/IT) for a high-efficiency video coding (HEVC) decoder. Our highly parallel and pipelined architecture was designed to support all HEVC Transform Unit (TU) sizes: 4 × 4, 8 × 8, 16 × 16, and 32 × 32. The IQ/IT was described in the VHSIC hardware description language and synthesized to Xilinx XC7Z020 field-programmable gate array (FPGA) and to TSMC 180 nm standard-cell library. The throughput of the hardware architecture reached in the worst case a processing rate of up to 1080 p at 33 fps at 146 MHz and 1080 p at 25 fps at 110 MHz when mapped to FPGA and standardcells, respectively. The validation of our architecture was conducted on the ZC702 platform using a Software/Hardware (SW/HW) enviro nment in order to evaluate different implementation methods (SW and SW/HW) in terms of power consumption and run-time. The experimental results demonstrate that the SW/HW accelerations were enhanced by more than 70% in terms of the run-time speed relative to the SW solution. Besides, the power consumption of the SW/HW designs was reduced by nearly 60% compared with the SW case.

A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing

Stochastic computing (SC) has been applied on the implementations of complex arithmetic functions. Complicated polynomial-based approximations lead to large hardware complexity of previous SC circu ...

An Intelligent Speed Limit Sign Recognition Approach Towards an Embedded Driver Assistance System

Road traffic safety has become a significant global public health issue. The number of traffic crashes is increasing in alarming proportions, leading to a large number of deaths and injuries. Most road accidents occur due to human errors including exceeding speed limit and failure to abide by driving rules. Therefore, in order to solve this issue, advanced driver-assistance systems are more and more in use thanks to their capabilities in minimizing the human error. These systems are used to enhance or adapt some or all of the tasks involved in operating a vehicle. Designers rely heavily on Artificial Intelligence in order to operate these systems. In this framework, this paper discusses the development of an intelligent speed limit signs’ recognition system, which can substantially enhance road safety. Since this system is conceived to be implanted on an FPGA card, the main challenges consist in achieving a high recognition rate with a low complexity level in the proposed algorithm. This will undoubtedly lead up to an optimized hardware architecture suitable for real time processing. For this purpose, a two-step based vision speed limit signs’ detection and recognition system has been proposed. The first step concerns sign candidate’s detection based on color and shape analysis; it consists in different sub image processing levels. The second step deals with the recognition and identification of the detected signs. To this end, several Machine Learning algorithms and several architectures of multilayer Neural Network and Wavelet Neural Network have been evaluated. The analysis of performance results and comparison with other widely used techniques have shown the effectiveness and efficiency of the proposed technique in terms of percentage of correct classification and execution time even for images captured under varied orientations and varied illumination conditions.

An Optimized Approach to Pipelined Architecture for Fast 2D Normalized Cross-Correlation

An optimized hardware architecture for fast normalized cross-correlation (NCC) is essential in real-time high-speed applications. Typical applications of NCC are in object localization, as one of the best motion estimators and as a similarity measure in the field of image processing. However, high computational cost is a significant drawback of NCC. To reduce computation time and hardware resource usages, this paper presents a feed-forward single-path architecture with parallel computation of numerator and denominator components of NCC. The cross-correlation of two signals is implemented in the frequency domain using pipelined architecture of 2D FFT with polyphase sequential subband decomposition technique. The FFT can be determined for any even length of signal when compared to the traditional method involving a power of two-signal length. The proposed pipelined architecture of NCC is more efficient in terms of computational complexity and memory requirement. This proposed architecture is implemented in Verilog HDL with fixed-point data type which helps to devise simple and efficient architecture, which gives excellent SQNR of more than 90 dB with 22-bit output word length. It can operate at the maximum clock frequency of 220.4[Formula: see text]MHz, takes a total NCC time of 4.36[Formula: see text][Formula: see text]s and has a latency of 996 cycles, giving a throughput of 220 Msamples/s for a block size of [Formula: see text] pixels using Virtex-7 FPGA. This pipelined architecture not only offers an attractive solution for different sizes of image block, but also improves the speed of the system.

FPGA-based implementation of intra prediction module for HEVC decoder

The High Efficiency Video Coding (HEVC) is the new standard which is designed to support High Definition (HD) and Ultra-HD video cotenants. In HEVC, several new coding tools are adopted in order to improve the coding efficiency and compression ratio but with a significant increase in the computational complexity comparing to the previous standard H.264/AVC. In this paper, we focus on reducing the complexity of the most consuming block in the HEVC decoder standard which is the intra prediction module. In this context, we propose an optimized hardware architecture dedicated to support the 34 modes of intra prediction module considering 4×4, 8×8 and 16×16 block sizes. The proposed design exploits the symmetric property between horizontal and vertical modes. Hence, we implement a new hardware architecture that factorizes the same hardware resources for both directions which leads to save the hardware cost, the power consumption and the processing time. Furthermore, the different block sizes are implemented independently in order to avoid memory overhead while accessing to the shared memory. The implemented design using Xilinx Zynq-based FPGA platform can process in real time the Ultra-HD video frame of resolution (4096×2048) at 232 MHz. As well, the synthesis results using the TSMC 180 nm CMOS technology provide similar performance than our FPGA implementation. Finally, the HW/SW implementation of full HEVC decoder can process the decoding of 15 FPS in best case for 240p video resolution with a gain of 60% in power consumption.

Avionics Graphics Hardware Performance Prediction with Machine Learning

Within the strongly regulated avionic engineering field, conventional graphical desktop hardware and software application programming interface (API) cannot be used because they do not conform to the avionic certification standards. We observe the need for better avionic graphical hardware, but system engineers lack system design tools related to graphical hardware. The endorsement of an optimal hardware architecture by estimating the performance of a graphical software, when a stable rendering engine does not yet exist, represents a major challenge. As proven by previous hardware emulation tools, there is also a potential for development cost reduction, by enabling developers to have a first estimation of the performance of its graphical engine early in the development cycle. In this paper, we propose to replace expensive development platforms by predictive software running on a desktop computer. More precisely, we present a system design tool that helps predict the rendering performance of graphical hardware based on the OpenGL Safety Critical API. First, we create nonparametric models of the underlying hardware, with machine learning, by analyzing the instantaneous frames per second (FPS) of the rendering of a synthetic 3D scene and by drawing multiple times with various characteristics that are typically found in synthetic vision applications. The number of characteristic combinations used during this supervised training phase is a subset of all possible combinations, but performance predictions can be arbitrarily extrapolated. To validate our models, we render an industrial scene with characteristic combinations not used during the training phase and we compare the predictions to those real values. We find a median prediction error of less than 4 FPS.

Optimized hardware accelerators for data mining applications on embedded platforms: Case study principal component analysis

With the proliferation of mobile, handheld, and embedded devices, many applications such as data mining applications have found their way into these devices. However, mobile devices have stringent area and power limitations, high speed-performance, reduced cost, and time-to-market requirements. Furthermore, applications running on mobile devices are becoming more complex requiring high processing power. These design constraints pose serious challenges to the embedded system designers. In order to process the applications on mobile and embedded systems, effectively and efficiently, optimized hardware architectures are needed. We are investigating the utilization of FPGA-based customized hardware to accelerate embedded data mining applications including handwritten analysis and facial recognition. For these biometric applications, Principal Component Analysis (PCA) is applied initially, followed by similarity measure. In this research work, we introduce novel and efficient embedded hardware architectures to accelerate the PCA computation. PCA is a classic technique to reduce the dimensionality of data by transforming the original data set into a new set of variables called Principal Components (PCs) that represent the key features of the data. We propose two hardware versions for PCA computation, each with its unique optimization techniques to enhance the performance of our designs, and one specifically with additional techniques to reduce the memory access latency of embedded platforms. To the best of our knowledge, we could not find similar work for PCA, specifically catered to the embedded devices, in the published literature. We perform experiments to evaluate the feasibility and efficiency of our designs using a benchmark dataset for biometrics. Our embedded hardware designs are generic, parameterized, and scalable; and achieve 78 times speedup as compared to its software counterparts.

Online stereo camera calibration for automotive vision based on HW-accelerated A-KAZE-feature extraction

Abstract Nowadays ongoing integration of camera based advanced driver assistance systems (ADAS) in vehicles demands increasingly complex digital image processing in order to interpret the surrounding situations. To ensure a timely reaction for obstacles lying ahead, far reaching depth information of the observed scene is necessary. Using stereo camera systems, this is achievable by enlarging the camera base line. With rapid driving, the exact alignment of the stereo images is no longer ensured due to vibrations of the vehicle. Based on detection, extraction and matching of Accelerated-KAZE image features (A-KAZE), the geometric distortions are compensable by estimating the external camera parameters for image rectification. The indispensable frame rate for applications in vehicles and the limited power budget in combination with the SW-flexibility demanded for future ADAS applications requires the usage of optimized hardware architectures. Thus, an online camera calibration based on an HW-accelerated A-KAZE extraction is introduced in this work. The suitability of A-KAZE features for an online camera calibration is proven. Furthermore, the Tensilica Vision P5-processor is evaluated regarding its suitability for real-time A-KAZE feature extraction. This processor provides a comprehensive instruction-set extension for high-performance digital image processing. While preserving the initial A-KAZE accuracy, a feature descriptor length reduction of factor × 3.8 is attained compared to the initial descriptor size and an estimated frame rate of 20 fps is achieved for A-KAZE feature extraction on the Tensilica Vision P5-processor.

Redundant Bit Security in RFIDs: Architecture Design and Security Performance Evaluation

This paper presents an analysis of the security performance and evaluation of the hardware architecture of the redundant bit security (RBS) cryptosystem. RBS is a lightweight symmetric encryption algorithm that targets resource-constrained RFID devices. Unlike the existing cryptosystems, RBS simultaneously provides confidentiality, authentication, and integrity of the plaintext by inserting hash-generated redundant bits among the already modified plaintext data. A flexible-length hash algorithm in our optimized hardware architecture allows RBS to support different key sizes which allows flexibility in the security level. Our analysis shows the resilience of RBS against powerful and well-known attacks such as differential attacks and known-plaintext attacks. We compare the performance of the RBS cryptosystem against other distinguished ciphers developed for RFID systems. Simulation results show that RBS results in approximately 100%, 239%, and 153% higher hardware efficiencies while requiring 48%, 56%, and 59% less energy-per-bit compared to H-PRESENT, HB-2, and Grain, respectively. Such results present confirmatory evidence that RBS is a superior solution for providing security in resource-constrained systems such as RFID systems especially when authentication is a priority.

Efficient Hardware Implementation of Ultralightweight RFID Mutual Authentication Protocol

Security and privacy are the two major concerns of radio-frequency identification (RFID) based identification systems. Several researchers have proposed ultralightweight mutual authentication protocols (UMAPs) to ensure the security of the low cost RFID tags in recent years. However, almost all of the previously proposed protocols have some serious security flaws and are vulnerable to various security attacks (full disclosure attack, desynchronization attack, impersonation attack, etc.). Recently, a more sophisticated and robust UMAP: Robust confidentiality integrity and authentication (RCIA)1 [U. Mujahid, M. Najam-ul-Islam and M. Ali Shami, RCIA: A new ultralightweight RFID authentication protocol using recursive hash, Int. J. Distrib. Sens. Netw. 2015 (2015) 642180] has been proposed. A new ultralightweight primitive, “recursive hash” has been used extensively in the protocol design which provides hamming weight unpredictability and irreversibility to ensure optimal security. In addition to security and privacy, small chip area is another design constraint which is mandatory requirement for a protocol to be considered as ultralightweight authentication protocol. Keeping in view the scenario presented above, this paper presents the efficient hardware implementation of the RCIA for EPC-C1G2 tags. Both the FPGA and ASIC implementation flows have been adopted. The FPGA design flow is primarily used to validate the functionality of the proposed hardware design whereas ASIC design (using TSMC 0.35 μm library) is used to validate the gate count. To the best of our knowledge, this is the first FPGA and ASIC implementation of any ultralightweight RFID authentication protocol. The simulation and synthesis results of the proposed optimal hardware architecture show the compatibility of the RCIA with extremely low cost RFID tags.

A simplified rectification method and its hardware architecture for embedded multimedia systems

Stereo vision, a future disruptive technology for obtaining three-dimensional distance information, can be applied to various embedded multimedia systems. Reducing the computational overhead of stereo vision necessitates the pre-processing procedure of rectification. For the implementation of rectification, several studies have proposed a look-up table- and computational logic-based approaches. However, the former exhibits excessive growth of memory with an increasing resolution of the image, and the latter requires numerous hardware resources for implementing the necessary computational logic. Thus, this paper proposes a simplified rectification calculation method and its optimized hardware architecture. By replacing matrix multiplications of the conventional method with simple accumulations and removing division operations, the proposed method reduces addition, multiplication, and division operations by 50, 100, and 100 %, respectively, compared with the conventional method. Although the experimental results show negligible differences between rectification by the conventional method and that by the proposed method, the latter consumes fewer hardware resources. Therefore, the proposed method and its architecture are more practical for real-time embedded multimedia systems.