An Optimized Approach to Pipelined Architecture for Fast 2D Normalized Cross-Correlation

Abstract

An optimized hardware architecture for fast normalized cross-correlation (NCC) is essential in real-time high-speed applications. Typical applications of NCC are in object localization, as one of the best motion estimators and as a similarity measure in the field of image processing. However, high computational cost is a significant drawback of NCC. To reduce computation time and hardware resource usages, this paper presents a feed-forward single-path architecture with parallel computation of numerator and denominator components of NCC. The cross-correlation of two signals is implemented in the frequency domain using pipelined architecture of 2D FFT with polyphase sequential subband decomposition technique. The FFT can be determined for any even length of signal when compared to the traditional method involving a power of two-signal length. The proposed pipelined architecture of NCC is more efficient in terms of computational complexity and memory requirement. This proposed architecture is implemented in Verilog HDL with fixed-point data type which helps to devise simple and efficient architecture, which gives excellent SQNR of more than 90 dB with 22-bit output word length. It can operate at the maximum clock frequency of 220.4[Formula: see text]MHz, takes a total NCC time of 4.36[Formula: see text][Formula: see text]s and has a latency of 996 cycles, giving a throughput of 220 Msamples/s for a block size of [Formula: see text] pixels using Virtex-7 FPGA. This pipelined architecture not only offers an attractive solution for different sizes of image block, but also improves the speed of the system.