Operational Transconductance Amplifier Research Articles

Design of Two Stage OTA based Sixth Order Butter-worth Low Pass Filter using CMOS 180nm Technology

This paper shows the design of 6th order Butter-worth low pass filter based on operational trans-conductance amplifier (OTA). The designing and simulation results are obtained using Cadence Virtuoso tool with 180nm (0.18μm) technology. The simulation results of OTA have a gain of about 97.3dB. The simulation results of butter-worth low pass filter for 1.25V supply voltage and 20μA biasing current gives -96.4mdB gain and 2.9GHz bandwidth for a frequency range of 100Hz to 10GHz. The results are presented in this paper.

Cell-Based Synthesis of Multiple Analog Filter and Oscillator Topologies Employing Graph

A new synthesis methodology, which offers design harmony of multiple analog filter and oscillator topologies is presented. Vertices of a bipartite graph are defined with simple mathematical function, denoted as cell. Weight of the edges are denoted by relation operator. A general theory has been developed based on graph and a set of traversal rules conjugated with cell, to produce multiple number of second-order function (SOF) in terms of cells. Theoretical approach has been facilitated with operational transconductance amplifier (OTA)-based circuit realization of multiple filter and oscillator topologies, and abridged with algorithm, which may lead to virtual EDA tool and field programmable analog array (FPAA). The proposed synthesis approach is validated with SPICE simulation.

An Energy-Efficient BJT-Based Temperature Sensor with ±0.8 °C (3σ) Inaccuracy from −50 to 150 °C

This article presents an energy-efficient BJT-based temperature sensor. The output of sensing front-ends is modulated by employing an incremental Δ-Σ ADC as a readout interface. The cascoded floating-inverter-based dynamic amplifier (FIA) is used as the integrator instead of the conventional operational transconductance amplifier (OTA) to achieve a low power consumption. To enhance the accuracy, chopping and dynamic element matching (DEM) are applied to eliminate the component mismatch error while β-compensation resistor and optimized bias current are used to minimize the effect of β variation. Fabricated in a standard 180-nm CMOS process, this sensor has an active area of 0.13 mm2. While dissipating only 45.7 μW in total, the sensor achieves an inaccuracy of ±0.8 °C (3σ) from -50 °C to 150 °C after one-point calibration.

Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs

The design and optimization of the analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are intrinsically complicated and depend heavily on the designer’s experience, and are associated with very long design and optimization-cycle times. In addition, in order to the analog and radiofrequency (RF) CMOS IC work suitably in practice, it is necessary to perform robustness analyses (RAs) through Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, which result in still-higher design and optimization cycle times and therefore represent the biggest bottleneck to the launching of new electronic products. In this context, this manuscript aims to present, for the first time, the use of a custom imperialist competitive algorithm (ICA) in order to reduce the design and optimization-cycle times of analog CMOS ICs. In this study, we implement some Miller CMOS operational transconductance amplifiers (OTAs) using the computational tool named iMTGSPICE, considering two different bulk CMOS IC manufacturing processes from Taiwan Semiconductor Company (TSMC) (180 nm and 65 nm nodes) and two evolutionary optimization methodologies of artificial intelligence, i.e., ICA and a genetic algorithm (GA). The main result obtained by this work shows that, by using an ICA-customized evolutionary algorithm to perform the design and optimization processes of Miller CMOS OTAs, it is possible to reduce the design and optimization-cycle times by up to 83% in relation to those implemented with the GA-customized evolutionary algorithm, achieving practically the same electrical performance.

A Differential-to-Single-Ended Converter Based on Enhanced Body-Driven Current Mirrors Targeting Ultra-Low-Voltage OTAs

In this work, an ultra-low-voltage (ULV) technique to improve body-driven current mirrors is proposed. The proposed technique is employed to improve the performance of conventional differential-to-single-ended (D2S) converters which at these low voltages suffer from a low common-mode rejection ratio (CMRR). In addition, the technique aims to improve the performance of the conventional D2S also under a large signal swing and with respect to the process, voltage and temperature (PVT) variations, resulting in a very low distortion, high current mirror accuracy and robust performance. An enhanced body-driven current mirror was designed in a 130nm CMOS technology from STMicroelectronics and an exhaustive campaign of simulations was conducted to confirm the effectiveness of the strategy and the robustness of the results. The enhanced D2S was also employed to design a ULV operational transconductance amplifier (OTA) and a comparison with an OTA based on a conventional D2S was provided. The simulation results have shown that the proposed enhanced D2S allows achieving the ULV OTAs with a CMRR and a PSRR which are 18 and 9 dB higher than the ones obtained with the conventional D2S topology, respectively. Moreover, the linearity performance is also improved as shown by the THD, whose value is decreased of about 5 dB.

Two New Voltage-Mode Sinusoidal Quadrature Oscillators Employing Second-Generation Voltage Conveyors

This article presents an application of a second-generation voltage conveyor (VCII) as a quadrature oscillator. The controlling parameters of the presented circuits, i.e. oscillation condition and oscillation frequency are tuneable without affecting the other. Both the single-resistance-controlled oscillators employ only two VCII, two grounded capacitors, and three grounded/ virtually grounded resistors. To strengthen the design idea regular mathematical analysis such as ideal, non-ideal, parasitic, frequency stability, phase noise analysis, and sensitivity calculations have been performed. To validate the proposed networks, the simulations have been carried out using 180 nm CMOS technology parameters, and experimental studies have also been performed using commercially available integrated circuits.

FinFET-based non-linear analog signal processing modules

FinFETs exhibit far superior transistor characteristics (better gate control and a lower sub-threshold slope) as compared to the standard MOSFETs, this paper first employs the FinFETs in the design of an operational transconductance amplifier (OTA). The FinFET-based OTA offers a linearity range and - 3 dB bandwidth of ± 300 mV and 631.81 GHz, respectively. Further, the non-linear applications of the proposed OTA, viz. voltage divider, memristor emulator, and a memristive neuron, are presented. The proposed analog voltage divider circuit contains one OTA and two external N-FinFETs. The maximum bandwidth obtained for the voltage divider is 217.54 GHz. The memristor emulator contains one OTA, two external N-FinFETs, and one grounded capacitor. The proposed emulator circuit follows the signature characteristics of the actual memristor device. The frequency response characteristics of the proposed emulator circuit depict a bandwidth of 22.7 GHz. The proposed emulator shows non-volatile as well as electronically tunable features. Next, Monte-Carlo simulation analysis has been performed on the proposed circuits in order to observe the effects of statistical variation in different operating conditions. Furthermore, we propose a FinFET-based passive memristive neuron model using a memristor emulator circuit. The proposed neuron circuit follows a tangent hyperbolic activation function. All the proposed circuits are suitable for monolithic implementation. The proposed circuits are verified using 20 nm FinFET technology. The simulation results obtained using HSPICE agree well with the theoretical analysis.

A very low-power discrete-time delta-sigma modulator for wireless body area network

This paper proposes a very low-power discrete-time delta-sigma modulator (DTDSM) for the wireless body area network (WBAN) which deals with biomedical signals. The first stage integrator is optimized using correlated double sampling technique and is implemented using a high-gain designed telescopic operational transconductance amplifier (OTA) in order to maintain the proposed second-order DTDSM high resolution. In order to keep both stage integrators active and prevent ENOB loss, a very low power two-stage charge-steering amplifier is employed in the second stage integrator which leads to a power efficient design. Due to not high but enough voltage-gain of this type of amplifier, the proposed charge-steering-based integrator leads to a negligible loss of ENOB in comparison to passive integrators with no voltage gain which are commonly used in the second stage to reduce the total power. In fact, due to the combination of a high-gain OTA in first stage integrator and a low-power charge-steering amplifier in second stage, compromise between high resolution and low power consumption will be depicted.The proposed DTDSM is designed for a signal bandwidth of 50 kHz with an oversampling ratio of 128 for implantable biomedical devices in the MICS band. Simulations are done using TSMC 180 nm technology at a 1.8 V power supply. Simulation results illustrate that the designed modulator achieves an SNR of 56 dB which is equal to 9 bits of ENOB that is in the desired range for biomedical signals. The power consumption of this modulator is only 142 μW at a 12.5 MHz sampling frequency.

Design of Two stage OTA with Optimised Compensation Capacitance

A two-stage operational transconductance amplifier is constructed and compared between 45nm and 180nm CMOS technology in this paper. To find the best design, the suggested operational amplifier is examined across a number of distinct parameters. With a supply voltage of 1.8V, it reaches a maximum gain of about 66 dB and a phase margin of 82°. A Cadence Virtuoso-based circuit simulator has been used to construct the suggested operational amplifier and the comparison is done. Keywords: OTA, Miller coupling capacitance, cadence virtuoso, Gain, output swing, power dissipation.

Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier

This article presents a delta–sigma modulator (DSM) using a cascoded floating-inverter-based dynamic amplifier. The proposed cascoded dynamic amplifier achieves more than 50-dB dc gain while maintaining an HD3 of better than –110 dBc for signal swings less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$300~\mathrm {mV_{ppd}}$ </tex-math></inline-formula> . Compared to the previously reported two-stage floating inverter amplifier (FIA), the cascoded FIA has a lower and a process invariant input-referred noise, making it an ideal choice for high-resolution ADCs. We also show that, when such a single-stage dynamic amplifier, which has a time-varying transconductance, is used in closed-loop switched-capacitor circuits, the settling bandwidth depends on the average transconductance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m,\rm avg}$ </tex-math></inline-formula> during the settling interval. A detailed analysis reveals that, when the floating inverter structure operates in weak inversion for most of the time (which is the power-efficient way to bias the amplifier), this average transconductance depends strongly on the reservoir capacitance value and only weakly on the transistor dimensions. Besides, it is less sensitive to temperature variations, unlike the transconductance of a conventional OTA biased in weak inversion. We also quantitatively derive and show that the cascoded FIA is more power-efficient than a conventional static-current biased operational transconductance amplifier. Using the cascoded FIA, a discrete-time DSM has been designed and fabricated in a 180-nm CMOS process. The modulator runs at 3.072 MHz while consuming 189 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> from a 1.8-V supply. In a bandwidth of 24 kHz, the measured SNR/SNDR/SFDR is 96.4/96.2/114 dB, respectively.

A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-μm CMOS

This article presents the experimental results for a multiple-input operational transconductance amplifier (MI-OTA). To achieve extended linearity under 0.5-V low voltage supply, the circuit employs three linearization techniques: the bulk-driven (BD), the source degeneration, and the input voltage attenuation created by the MI metal-oxide-semiconductor transistor technique (MI-MOST). Although the linearization techniques result in reduced dc gain, the self-cascode transistors are used to boost the gain of the MI-OTA. Furthermore, the MI-MOST simplifies the internal structure of the OTA and may reduce the complexity of the applications. The MI-OTA operates in the subthreshold region and offers tunability by a bias current in the nanoampere range. The circuit is capable to work with 0.5-V supply voltage while consuming 24.77 nW. The circuit was fabricated using the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology and it occupies a 0.01153-mm2 silicon area. Intensive simulation and experimental results confirm the benefits and robustness of the design.

Electronically tunable positive and negative fractional order inductor circuit using single topology

This article presents electronically tunable grounded and floating fractional order inductor circuits. The proposed circuits employ two operational transconductance amplifiers (OTAs), one fractional order capacitor, one inverter and four MOS switches and are capable to work in positive mode and negative mode without change in topology. The behaviour of the proposed circuit is also analyzed in presence of parasites that may appear in the practical circuit. The functional verification is done via pre and post layout simulations at 90 nm CMOS technology parameter. The usefulness of the proposed positive fractional inductor circuit is demonstrated through fractional order band pass filter and fractional order high pass ladder filter. The performance of the proposed negative fractional inductance circuit is demonstrated through a fractional inductance cancellation circuit.

Resistorless First-Order Universal Filter Structures Employing OTAs with Independent Controllability of Gain and Pole Frequency

This communication presents two new first order universal active filter configurations employing operational transconductance amplifiers (OTA) and use grounded capacitor which is prominently suitable for integrated chip (IC) fabrication. One of the proposed topologies provides voltage mode (VM) and transconductance mode (TCM) of operations while the other circuit provides current mode (CM) in addition with transresistance mode (TRM) filter functions. All three first order filter functions namely low pass filter (LPF), high pass filter (HPF) and all pass filter (APF) are configurable with appropriate choice(s) of input voltage/current signals. An equal transconductor condition (which can be easily achieved) is required for the realization of APF functions. The proposed filter configurations possess high input impedance and high output impedance and also offer independent electronic tunability of pole frequency/cut-off frequency. The gain of filters realized in VM, TCM and TRM has independent electronic tunability feature and can be adjusted through transconductor. For the usability of proposed filters, multi-phase sinusoidal oscillator has also been demonstrated. To assure the workability of the proposed filter structures, PSPICE simulations with CMOS OTA implemented in 0.18 µm TSMC technology parameters has been used. Various simulation results including Monte-Carlo simulations, process corner analysis, total harmonic distortions (%THD) and temperature analysis have also been appended. Experimental results employing off-the-shelf IC LM13700 type OTAs have also been included to verify the theoretical propositions of first order universal filters and multiphase sinusoidal oscillators.

A Lossless Active Inductor Design Using Single ZC-VDCC: Grounded and Floating Mode

This research paper includes two different topologies for the operation of both grounded and floating active inductor (AI) realization. Both structures use a single Z-Copy Voltage Differencing Current Conveyor (ZC-VDCC) and an external grounded capacitor (C). The operational behavior of the proposed design is free from the component matching constraint. In addition, an application workability of the AI is tested for filter frequency response that comprises band pass filter (BPF) and band rejection filter (BRF) using grounded as well as floating active inductor, respectively. The performance test of the proposed active inductor is successfully validated in SPICE computer simulation using 0.18 µm TSMC parameter for ZC-VDCC. Moreover, an experimental verification is also performed using easily available Current Feedback Operational Amplifier (CFOA/IC-AD844) and Operational Transconductance Amplifier (OTA/IC-CA3080) for the implementation of ZC-VDCC. Both simulation and experimental observation are well verified to justify the theoretical concept behind the proposed AI.

New memristor-less, resistor-less, two-OTA based grounded and floating meminductor emulators and their applications in chaotic oscillators

This paper presents a simple realization of the meminductor emulator using two operational transconductance amplifiers (OTAs) and two capacitors. To obtain different configurations of meminductor in the proposed design, one of the OTA has been replaced by a multi-output transconductance amplifier (MO-OTA). MO-OTA is a slightly modified version of conventional OTA that has multiple outputs. The design flexibilities offered by MO-OTA helped in achieving decremental as well as incremental configurations for both grounded and floating meminductor emulators. The proposed meminductor emulator realizations are very simple because these emulators do not employ an analog multiplier, resistor, or memristor. The pinched hysteresis curves have been acquired for the frequency range of 600 kHz–900 kHz for different values of capacitors. The proposed meminductor emulators have been designed and simulated with the help of the LTspice tool using TSMC 180 nm CMOS technology parameters. The pinched hysteresis loops, transient analysis, and non-volatility tests of the proposed meminductor emulators confirm their satisfactory behavior as meminductor. The functioning of proposed meminductor emulator circuits has also been tested by demonstrating their use in chaotic oscillators.

Impedance-mode capacitance multiplier with OTA-based flipped voltage follower for high accuracy and large multiplication factor

A capacitance multiplier with large multiplication factor, increased accuracy, and class AB operation is presented. The multiplier is an impedance mode implementation consisting of a Flipped Voltage Follower based on Operational Transconductance Amplifiers (OTA). This gives the possibility to offer rail-to-rail operation and class AB operation to drive demanding loads depending on the application. In addition, one of the OTAs is designed to offer a transconductance gain based on passive resistors and achieve increased accuracy in the multiplication factor by means of proper layout techniques. The circuit was implemented in a 0.5µm technology and has multiplication factors of 10, 100, 1k and 10k, a power dissipation of 0.56mW and a silicon area of 0.059mm2. Simulation and experimental results of the multiplier demonstrate the proper operation.

A 0.7V 1.6mW fractional-N synthesizers for BLE RF transceiver in 40nm CMOS

This paper presents a low-power fractional-N synthesizer for BLE with a gate-switching charge pump (CP) and high-speed prescaler. To reduce the current mismatch under low supply voltage, a master-slave rail-to-rail operational trans-conductance amplifier (OTA) structure is employed to the CP; Current self-matching technique guarantees the charging current is equal to discharging current. The embedded logic gates and power switch technique are employed to true-single-phase-clock (TSPC) to reduce power consumption and improve the operating speed of the divider. Random dither is injected into the ΔΣ modulator to prolong the period of output sequence. The proposed phase-locked loop (PLL) is implemented in the 40-nm CMOS process. It achieves -85.94dBc/Hz@100kHz and -109.18dBc/Hz@1MHz in fractional-N mode while consuming 1.6mW under a 0.7V voltage supply.

Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (𝐹𝑜𝑀s) are the highest when compared to other reported FCOTAs in the literature.

Simulation Based Analysis of Low-Voltage-Tunable Biquad Filter Using Operational Transconductance Amplifiers

ABSTRACT A CMOS realisation of a voltage tunable biquad filter using only MOSFET-based operational transconductance amplifier (OTA) and capacitors has been designed using silicon-based CMOS technology. It operates at a low supply voltage of 0.25 V at a 500 MHz frequency. The filter is theoretically analysed and then simulated using commercially available Cadence Virtuoso tools at 0.18 μm CMOS technology parameters. The proposed design is used to implement second-order low pass, highpass, bandpass, and bandreject filters with the same circuit simply by tuning the input voltage. The bandwidth and cut-off frequency also can be changed by changing the capacitor values.

Synthetic Transformer using Operational Transconductance Amplifier (OTA) and Voltage Differencing Current Conveyor (VDCC)

This paper presents a new realization of synthetic transformer using off the shelf active blocks. This proposed transformer is designed using operational transconductance amplifier (OTA), voltage differencing current conveyor (VDCC), resistor and capacitor. Use of VDCC helps to utilizes benefits of both voltage differencing unit and current conveyor. The working of proposed circuit is verified through simulations in LTSPICE using TSMC 180nm process characteristics. The proposed circuit offers the feature of adjusting primary and secondary self-inductances and mutual inductance independently. The bias current of the VDCC is used to control the primary and secondary self-inductance and mutual inductance of synthetic transformer.