64-bit Operands Research Articles

Distributed arithmetic-FIR filter design using Approximate Karatsuba Multiplier and VLCSA

In this manuscript, a High Throughput and Low Latency DA-FIR filter design is integrated with Approximate Karatsuba Multiplier (AKM) and Variable Latency Carry Skip Adder (VLCSA) is proposed for the noise removal application in SDR. In this design, an AKM and VLCSA are considered to decrease the count of partial products on DA framework, although no multiplication is clearly performed. Thus, an important reduction is accomplished under accumulation circuits. The main execution problem of the DA system is the size of lookup table (LUT) increases exponentially through the length of inner product. To further diminish the memory complexity, approximate DA architectures depending truncation approach are needed. Partial products on DA are created through truncating least significant bits (LSBs) of inputs. The proposed hybrid technique lessens a count of LUTs by truncating the least significant bits of input operands. To further reduce the latency, this manuscript deals with one of the fastest multipliers, namely Approximate Karatsuba Multiplier employed for accumulation of partial products. The proposed design is performed in Verilog using Xilinx 14.5 ISE simulation. The experimental performances of the proposed DA-FIR-Hyb AKE-VLCSA filter is evaluated under lower delay, lower static power and compared with the existing filters.

Design of Area efficient comparator architecture using 5T XOR GATE

The use of comparators in computation-based designs is extensive, making optimization crucial. While some comparator designs use dynamic logic to achieve low-power consumption, the limitations of low-speed and poor-noise margin make this approach challenging. The proposed comparator design offers a new solution that is both area-efficient and has a high operating speed while consuming low-power. It was designed using 180nm technology in Tanner Tool, and its results were observed. Overall, this work presents a promising new solution for optimizing digital comparators and improving the efficiency and speed of computation-based designs. This work presents a new solution for optimizing N-bit digital comparators in terms of area, power, and speed. The proposed comparator structure is a clever design that consists of two crucial modules - the comparison evaluation module (CEM) and the final module (FM). The CEM is responsible for evaluating the comparison, and it uses a regular structure of repeated logic cells to implement a parallel prefix tree structure. This approach is independent of input operand bit widths, which makes it highly versatile and adaptable to different applications. The FM, on the other hand, validates the final comparison based on the results obtained from the CEM. This ensures that the final output is accurate and reliable. By utilizing these two modules, the proposed comparator structure is able to achieve high-precision comparisons while maintaining a relatively simple and efficient design. Overall, this comparator structure is a promising development in the field of digital circuit design, and it has the potential to improve the performance and reliability of a wide range electronic systems.

A High-Performance Elliptic Curve Cryptographic Processor of SM2 over GF(p)

Elliptic curve cryptography (ECC) is widely used in practical applications because ECC has far fewer bits for operands at the same level of security than other public-key cryptosystems such as RSA. The performance of an ECC processor is usually determined by modular multiplication (MM) and point multiplication (PM) operations. For recommended prime field, MM operation can consist of multiplication and fast reduction operations. In this paper, a 256-bit multiplication operation is implemented by a 129-bit (half-word) multiplier using Karatsuba–Ofman multiplication algorithm. The fast reduction is a modulo operation, which gets 512-bit input data from multiplication and outputs a 256-bit result ( 0 ≤ Z < p ) . We propose a two-stage fast reduction algorithm (TSFR) over SCA-256 prime field, which can obtain an intermediate result of 0 ≤ Z < 2 p instead of 0 ≤ Z < 14 p in traditional algorithm, avoiding a lot of repetitive subtraction operations. The PM operation is implemented in width nonadjacent form (NAF) algorithm and its operational schedules are improved to increase the parallelism of multiplication and fast reduction operations. Synthesized with a 0.13 μ m complementary metal oxide semiconductor (CMOS) standard cell library, the proposed processor costs an area of 280 k gates and PM operation takes 0.057 ms at the frequency of 250 MHz. The design is also implemented on Xilinx Virtex-6 platform, which consumes 27.655 k LUTs and takes 0.37 ms to perform one 256-bit PM operation, attaining six times speed-up over the state-of-the-art. The processor makes a tradeoff between area and performance, thus it is better than other methods.

A Parallel and Uniform $k$-Partition Method for Montgomery Multiplication

A way to speed up the Montgomery Multiplication by distributing the multiplier operand bits into <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\mbi {k}}$</tex> </formula> partitions is proposed. All of them process in parallel and use an identical algorithm. Each partition executes its task in <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\mbi {n/k}}$</tex> </formula> steps. Even though the computationstep operates in radix <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\mbi {2^k}}$</tex> </formula> , the complexity is reduced by the use of a limited digit set. Experiments with a 90-nm cell library show that the hardware cost and its complexity have a linear growth according to the number of partitions. Besides the gain in speed, the proposal reduces power consumption for multiplication operands with 256, 512, 1024, and 2048 bits. The uniform treatment of partition hardware design enables the realization of a fault-tolerant hardware.

High-performance computing VLSI system for bit-parallel exponentiation in GF(2m)

Finite or Galois fields are used in numerous applications like error correcting codes in digital communication, pseudorandom number generation and cryptography. These applications often require computing exponentiation in which is a very computationally intensive operation. This article presents a high-performance computing method for performing exponentiation in . The key contribution of this article is to extend the bit-parallel structure for multiplication and division where bits of operands are processed at the same time, each bit traveling over a different path in the circuits to perform exponentiation. In addition, we also simplify the structure of parallel modules and pipelining stages in the proposed bit-parallel structure for exponentiation by considering the properties of and hardwiring many constant terms. The circuit architecture for the developed structure is shown for the example case of , and compared with existing approaches with respect to latency, hardware cost, area, delay, throughput and power dissipation for to . The results show that the proposed system has a low latency, hardware costs, area, delay and power dissipation that do not increase rapidly with increasing and a high throughput that does not decrease rapidly as increases compared with existing approaches.

An Efficient Look-up Table-based Approach for Multiplication over GF(2 m ) Generated by Trinomials

In this paper, we present an efficient look-up table (LUT)-based approach to design multipliers for GF(2 m ) generated by irreducible trinomials. A straightforward LUT-based multiplication requires a table of size (m×2 m ) bits for the Galois field of degree m. The LUT size, therefore, becomes quite large for the fields of large degrees recommended by the National Institute of Standards and Technology (NIST). Keeping that in view, we have proposed a digit-serial LUT-based design, where operand bits are grouped into digits of fixed width, and multiplication is performed in serial/parallel manner. We restrict the digit size to 4 to store only 16 words in the LUT to have lower area-delay complexity. We have also proposed a digit-parallel LUT-based design for high-speed applications, using the same LUT as the digit-serial design, at the cost of some additional multiplexors and combinational logic for parallel modular reductions and additions. We have presented a simple circuit for the initialization of LUT content, which can be used to update the LUT in three cycles whenever required. The proposed digit-serial design involves less area-complexity and less time-complexity than those of the existing LUT-based designs. The proposed digit-parallel design offers nearly 28 % improvement in area-delay product over the best of the existing LUT-based designs. NIST has recommended five binary finite fields for elliptic curve cryptography, out of which two are generated by the trinomials Q(x)=x 233+x 74+1 and Q(x)=x 409+x 87+1. In this paper, we have designed a reconfigurable multiplier that can be used for both these fields. The proposed reconfigurable multiplier is shown to have a negligible reconfiguration overhead and would be useful for cryptographic applications.

Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers

The development of algorithms from the communication and the signal processing domain often requires floating point arithmetic as well as support for trigonometric functions. While state-of-the-art digital signal processors offer hardware support for this kind of functions, embedded processors for mobile applications emulate floating point arithmetic and trigonometric functions in software. This emulation increases the number of required processing cycles compared to a dedicated hardware implementation. During development and implementation of ASIPs another problem with the emulation of these instructions arises. As the emulation has to be very flexible (e.g. variable operand bit width) emulation is carried out generally in a high level programming language leading to increased flexibility at the cost of reduced performance. This paper presents the design space exploration for an ASIP with an attached floating point co-processor in terms of performance and area and energy costs. To integrate the co-processor instructions, the ASIP's architecture description is modified and software development tools (e.g. assembler, linker and compiler) are adapted. Additionally, the ASIP's software libraries allow for a seamless integration of the co-processor instructions and enable ease of use for the application development. Power consumption and required silicon area can be decreased by choosing an application specific subset of supported co-processor functions and reduction of the co-processor's datapath bit width. The presented ASIP/co-processor architecture is functionally verified and area and power figures are derived for various configurations. A detailed analysis of the presented architecture used as a platform for GNSS receivers reveals promising configurations.

A New Systolic Architecture for Modular Division

A new systolic architecture for modular division is proposed in this paper. The architecture is based on a new hardware algorithm for modular division that is extended from the plus-minus algorithm for the greatest common divisor computation. Both the area complexity and the time complexity of the new architecture are linear with respect to the operand bit length. Compared to the architecture using a redundant number representation proposed by Kaihara and Takagi, the new architecture allows a doubled throughput due primarily to the greatly reduced critical path delay, while the area is only about 20 percent larger. Moreover, it is shown that, with a small addition to the control logic, the architecture can also be used to perform Montgomery modular multiplication, thereby efficiently realizing a unified modular multiplier/divider

Transient-fault recovery for chip multiprocessors

To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR). CRTR extends the previously-proposed CRT for transient-fault detection in CMPs, and the previously-proposed SRTR for transient-fault recovery in SMT. All these schemes achieve fault tolerance by executing and comparing two copies, called leading and trailing threads, of a given application. Previous recovery schemes for SMT do not perform well on CMPs. In a CMP, the leading and trailing threads execute on different processors to achieve load balancing and reduce the probability of a fault corrupting both threads; whereas in an SMT, both threads execute on the same processor. The inter-processor communication required to compare the threads introduces latency and bandwidth problems not present in an SMT.To hide inter-processor latency, CRTR executes the leading thread ahead of the trailing thread by maintaining a long slack, enabled by asymmetric commit. CRTR commits the leading thread before checking and the trailing thread after checking, so that the trailing thread state may be used for recovery. Previous recovery schemes commit both threads after checking, making a long slack suboptimal. To tackle inter-processor bandwidth, CRTR not only increases the bandwidth supply by pipelining the communication paths, but also reduces the bandwidth demand. By reasoning that faults propagate through dependences, previously-proposed Dependence-Based Checking Elision (DBCE) exploits (true) register dependence chains so that only the value of the last instruction in a chain is checked. However, instructions that mask operand bits may mask faults and limit the use of dependence chains. We propose Death- and Dependence-Based Checking Elision (DDBCE), which chains a masking instruction only if the source operand of the instruction dies after the instruction. Register deaths ensure that masked faults do not corrupt later computation. Using SPEC2000, we show that CRTR incurs negligible performance loss compared to CRT for inter-processor (one-way) latency as high as 30 cycles, and that the bandwidth requirements of CRT and CRTR with DDBCE are 5.2 and 7.1 bytes/cycle, respectively.

Register Allocation for Banked Register File

A banked register file is a register file partitioned into banks. A register in a banked register file is addressed with the register number in conjunction with the active bank number. A banked register file may be employed to reduce the number of bits for register operands in the instruction encoding at the cost of bank changes and inter-bank data transfers. Although a banked register file is introduced to provide sufficient registers and reduce memory traffic, it may on the other hand inflate code by unwanted bank hanges and excessive inter-bank data movements. In this context, code quality heavily depends on the register allocator that decides the location of each variable. This paper addresses a heuristic approach to register allocation for exploiting two register banks. It performs global register allocation with the primary bank registers, while reducing the register pressure by doing local register allocation with the secondary bank registers. Experimental results show that the proposed register allocator eliminates a significant amount of memory traffic while achieving smaller code size compared to an allocator that utilizes the primary bank only.

Comments on "A systematic approach for design of digit-serial signal processing architectures"

For the original paper see IEEE Trans. Circuits Syst., vol. 38, no. 4, p. 358-75 (1991). In the aforementioned paper, Parhi has modified the square-root algorithm and the relevant architecture presented by Majithia (1971). Although the example computed by the author, gives the correct result, for many other examples, the algorithm yields incorrect results because it is missing the necessary operand bits that must be included in each step of the add/subtract operation and must be transmitted to the next step. This lack of operand bits is due to the elimination of the msb of the partial remainder after shifting it by one bit to the left at each step.

Optical arithmetic unit using bit-WDM

A novel arithmetic unit is proposed consisting of a pipelined optical ripple carry adder that adds two words with bits multiplexed by different wavelengths on a single fiber. The addition result is returned to a fiber bus in the same format as the incoming words. The corresponding operand bit pairs are split off the fiber using wavelength division demultiplexers. Full adders compute the sum for each bit pair and the carry from the next lower significant bit pair. The full adder uses couplers and NOT, NOR and novel XOR logic gates constructed using semiconductor optical amplifiers for gain and wavelength shifting.

A novel design of a two operand normalization circuit

This paper presents a new design for two operand normalization. The two operand normalization operation involves the normalization of at least one of two operands by left shifting both by the same amount. Our design performs the computation of the shift by making an OR of the bits of both operands in a tree network, encoding the position of the first nonzero bit. The encoded position is obtained most significant bit first, and then there is an overlapping with the shifting operation. The design we propose replaces two leading zero detector circuits and a comparator, that are present in the conventional approach. Our scheme demonstrates to be more area efficient than the conventional one. The circuit we propose is useful in floating point complex multiplication and COordinate Rotation DIgital Computer (CORDIC) processors.

A flow-mode, self-steering, cellular multiplier-summation processor

Flow-mode or stream-processing digital systems have been proposed in which code, control and data are constantly moving so that multiple instructions are processed concurrently. We show the design of a flow-mode cellular array processor which can perform a number of two's complement fixed-point arithmetic operations. These operations are: three operand addition and/or subtraction, two operand multiplication and vector inner-product. Operand sizes are: 2N bit for addition and subtraction operands, andN bit for multiplication operands. Results are 2N bit. The network can simultaneously operate on 4N+2 datasets with any mix of the above operations being handled. The processor is based on the use of asynchronous cellular arrays. Given a continued flow of input datasets, the effective computation time is worst-case propagation time within one cell. A typical cell contains a 1-bit position 3-input full adder with associated input data storage. Thus the effective computation time is independent of the operand bit length.