High-performance computing VLSI system for bit-parallel exponentiation in GF(2m)

Abstract

Finite or Galois fields are used in numerous applications like error correcting codes in digital communication, pseudorandom number generation and cryptography. These applications often require computing exponentiation in which is a very computationally intensive operation. This article presents a high-performance computing method for performing exponentiation in . The key contribution of this article is to extend the bit-parallel structure for multiplication and division where bits of operands are processed at the same time, each bit traveling over a different path in the circuits to perform exponentiation. In addition, we also simplify the structure of parallel modules and pipelining stages in the proposed bit-parallel structure for exponentiation by considering the properties of and hardwiring many constant terms. The circuit architecture for the developed structure is shown for the example case of , and compared with existing approaches with respect to latency, hardware cost, area, delay, throughput and power dissipation for to . The results show that the proposed system has a low latency, hardware costs, area, delay and power dissipation that do not increase rapidly with increasing and a high throughput that does not decrease rapidly as increases compared with existing approaches.