Abstract
Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. These applications often require computing exponentiations in GF(2/sup m/) which is a very computationally intensive operation. The methods proposed in the literature achieve exponentiation by iterative methods using repeated multiplications and the hardware implementations use a number of Galois field multipliers in parallel resulting in expensive hardware. In this paper, we present a new algorithm based on a pattern matching technique for computing exponentiations in GF(2/sup m/), for values of m/spl les/8. A systolic array processor architecture was developed by the authors for performing multiplication and division in GF(2/sup m/) in [13]. A similar strategy is proposed in this paper for achieving exponentiation at the rate of a new result every clock cycle. A prototype VLSI chip Called ACE implementing the proposed architecture for Galois field GF(2/sup 4/) has been designed and verified using CMOS 2 /spl mu/m technology. The chip can yield a computational rate of 40 million exponentiations per second.
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