Hardware implementation of the binary method for exponentiation in GF(2/sup m/)

Abstract

Exponentiation in finite or Galois fields, GF(2/sup m/), is a basic operation for several algorithms in areas such as cryptography, error-correlation codes and digital signal processing. Nevertheless the involved calculations are very time consuming, especially when they are performed by software. Due to performance and security reasons, it is often more convenient to implement cryptographic algorithms by hardware. In order to overcome the well-known drawback of little or inexistent flexibility associated to traditional application specific integrated circuits (ASIC) solutions, we propose an architecture using field programmable gate arrays (FPGA). A cheap but still flexible modular exponentiation can be implemented using these devices. We provide the VHDL description of an architecture for exponentiation in GF(2/sup m/) based in the square-and-multiply method, called binary method, using two multipliers in parallel previously developed by ourselves. Our structure, compared with other designs reported earlier, introduces an important saving in hardware resources.