Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers

Abstract

The development of algorithms from the communication and the signal processing domain often requires floating point arithmetic as well as support for trigonometric functions. While state-of-the-art digital signal processors offer hardware support for this kind of functions, embedded processors for mobile applications emulate floating point arithmetic and trigonometric functions in software. This emulation increases the number of required processing cycles compared to a dedicated hardware implementation. During development and implementation of ASIPs another problem with the emulation of these instructions arises. As the emulation has to be very flexible (e.g. variable operand bit width) emulation is carried out generally in a high level programming language leading to increased flexibility at the cost of reduced performance. This paper presents the design space exploration for an ASIP with an attached floating point co-processor in terms of performance and area and energy costs. To integrate the co-processor instructions, the ASIP's architecture description is modified and software development tools (e.g. assembler, linker and compiler) are adapted. Additionally, the ASIP's software libraries allow for a seamless integration of the co-processor instructions and enable ease of use for the application development. Power consumption and required silicon area can be decreased by choosing an application specific subset of supported co-processor functions and reduction of the co-processor's datapath bit width. The presented ASIP/co-processor architecture is functionally verified and area and power figures are derived for various configurations. A detailed analysis of the presented architecture used as a platform for GNSS receivers reveals promising configurations.