Abstract

Elliptic curve cryptography (ECC) is widely used in practical applications because ECC has far fewer bits for operands at the same level of security than other public-key cryptosystems such as RSA. The performance of an ECC processor is usually determined by modular multiplication (MM) and point multiplication (PM) operations. For recommended prime field, MM operation can consist of multiplication and fast reduction operations. In this paper, a 256-bit multiplication operation is implemented by a 129-bit (half-word) multiplier using Karatsuba–Ofman multiplication algorithm. The fast reduction is a modulo operation, which gets 512-bit input data from multiplication and outputs a 256-bit result ( 0 ≤ Z < p ) . We propose a two-stage fast reduction algorithm (TSFR) over SCA-256 prime field, which can obtain an intermediate result of 0 ≤ Z < 2 p instead of 0 ≤ Z < 14 p in traditional algorithm, avoiding a lot of repetitive subtraction operations. The PM operation is implemented in width nonadjacent form (NAF) algorithm and its operational schedules are improved to increase the parallelism of multiplication and fast reduction operations. Synthesized with a 0.13 μ m complementary metal oxide semiconductor (CMOS) standard cell library, the proposed processor costs an area of 280 k gates and PM operation takes 0.057 ms at the frequency of 250 MHz. The design is also implemented on Xilinx Virtex-6 platform, which consumes 27.655 k LUTs and takes 0.37 ms to perform one 256-bit PM operation, attaining six times speed-up over the state-of-the-art. The processor makes a tradeoff between area and performance, thus it is better than other methods.

Highlights

  • Elliptic curve cryptography (ECC) was proposed in 1986 by Miller [1] and Koblitz [2] to solve the difficult problem of the elliptic curve discrete logarithm problem (ECDLP)

  • ECC can be implemented on three platforms: software, Field Programmable Gate Array (FPGA)

  • We propose a two-stage fast reduction algorithm over State Cryptography Administration (SCA)-256 given in Algorithm 3

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Summary

Introduction

Elliptic curve cryptography (ECC) was proposed in 1986 by Miller [1] and Koblitz [2] to solve the difficult problem of the elliptic curve discrete logarithm problem (ECDLP). Its fast reduction operation in SCA-256 prime field gets intermediate result Z (0 ≤ Z < 14p), which will cost thirteen subtraction operations to get the final result Z (0 ≤ Z < p) in the worst case. Traditional fast reduction algorithms are one-stage, which get intermediate result Z, such as Z ∈ [0, 14p) in [3], Z ∈ (−4p, 5p) in [6], followed by a lot of iterative addition or subtraction operations to get the final result within [0, p). TSFR performs fast reduction operations twice and gets the intermediate result Z (0 ≤ Z < 2p), avoiding a lot of iterations of subtraction operation to get the final result. A high-performance ECC architecture based on half-word multiplier is proposed.

Mathematical Background
SM2 Architecture
Modular Multiplication
Point Addition and Point Doubling
Hardware Implementation Result
Design
Findings
Conclusions

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