Comments on "A systematic approach for design of digit-serial signal processing architectures"

Abstract

For the original paper see IEEE Trans. Circuits Syst., vol. 38, no. 4, p. 358-75 (1991). In the aforementioned paper, Parhi has modified the square-root algorithm and the relevant architecture presented by Majithia (1971). Although the example computed by the author, gives the correct result, for many other examples, the algorithm yields incorrect results because it is missing the necessary operand bits that must be included in each step of the add/subtract operation and must be transmitted to the next step. This lack of operand bits is due to the elimination of the msb of the partial remainder after shifting it by one bit to the left at each step.