On-state Current Research Articles

Phosphorus-based heterojunction tunnel field-effect transistors: from atomic insights to circuit renovations.

Tunnel field-effect transistors (TFETs) are gaining interest for low-power applications, but challenges like poor drive current, delayed saturation, and ambipolarity can hinder their performance. This work proposes a dopingless heterojunction TFET (DL-HTDET) utilizing advanced materials, all based on phosphorus, to address these issues. Our approach involves a comprehensive and accurate analysis of the DL-HTDET's behavior. It employs a hybrid simulation technique integrating atomistic modeling, device simulation, and circuit design. For the first time, we use density functional theory to compute the electrical parameters of a two-dimensional material, 10-layer black phosphorus, configured in the armchair direction as the source region. InP serves as the pocket, while AlP, with its high bandgap, acts as the drain region to suppress ambipolarity. Key parameters, including bandgap, effective mass, mobility, static dielectric constant, and electron affinity, are utilized to simulate the device characteristics. Three mechanisms are considered in the device design: interband tunneling, intraband tunneling, and thermionic emission. The effect of pocket length (Lpocket) on performance is studied, and the impact of different types of interface trap charges, ranging from low to high density, is considered, and the optimized device demonstrates good durability. Additionally, the gate leakage current, which is crucial for static power consumption, is taken into account. The DC and analog/radio frequency performance of the device are evaluated. The optimized DL-HTDET achieves an ON-state current of 125 μA μm-1, a current switching ratio of 1016, an average subthreshold swing of 5.10 mV dec-1, and a transconductance of 1.47 mS μm-1. A 7T SRAM cell is implemented, demonstrating high noise margins, low delay, and ultra-low power consumption. These achievements underscore the potential of the proposed device for high-speed, ultralow power applications.

Inter-valley phonon scattering limited performance of n-channel WS2 monolayer transistors

Abstract In addition to the K conduction band valley of monolayer WS2, there is a remote Q valley located 0.1 eV above the K valley. We investigate the effects of intra- and inter-valley phonon scattering, including K ↔ Q inter-valley scattering, on monolayer WS2 device performance using a recursive Green’s function algorithm and the Büttiker probe scattering model. Our analysis reveals that ballisticity drops to 54% when only intra-valley phonon scattering is considered. When inter-valley phonon scattering (excluding K ↔ Q inter-valley scattering) is added, ballisticity decreases to 42%. This further declines to 12% with the inclusion of K ↔ Q inter-valley scatterings. Similarly, low-field mobility values decrease successively from 395 cm 2 ( V ⋅ s ) − 1 to 223 cm 2 ( V ⋅ s ) − 1 and then to 110 cm 2 ( V ⋅ s ) − 1 at a sheet density of 109 cm−2. The primary scattering mechanism responsible for this degradation is K → Q inter-valley acoustic phonon scattering, characterized by a high deformation potential of 7.3 × 10 8 eV cm − 1 and a low energy of 16.76 meV. Additionally, K → Q inter-valley scattering significantly populates the Q valley, which presents a higher potential barrier in the on-state conduction band profile, resulting in a lower on-state current. Our analysis shows that approximately 40% of the on-state total power dissipated within the device is due to phonon scattering effects, with the remainder being released through thermalization in the device’s contacts.

Improving the Performance of Arsenene Nanoribbon Gate-All-Around Tunnel Field-Effect Transistors Using H Defects.

We systematically study the transport properties of arsenene nanoribbon tunneling field-effect transistors (TFETs) along the armchair directions using first-principles calculations based on density functional theory combined with the non-equilibrium Green's function approach. The pristine nanoribbon TFET devices with and without underlap (UL) exhibit poor performance. Introducing a H defect in the left UL region between the source and channel can drastically enhance the ON-state currents and reduce the SS to below 60 mV/decade. When the H defect is positioned far from the gate and/or at the center sites, the ON-state currents are substantially enhanced, meeting the International Technology Roadmap for Semiconductors requirements for high-performance and low-power devices with 5 nm channel length. The gate-all-around (GAA) structure can further improve the performance of the devices with H defects. Particularly for the devices with H defects near the edge, the GAA structure significantly reduces the SS values as low as 35 mV/decade. Our study demonstrates that GAA structure can greatly enhance the performance of the arsenene nanoribbon TFET devices with H defects, providing theoretical guidance for improving TFET performance based on two-dimensional material nanoribbons through the combination of defect engineering and GAA gate structures.

Demonstration of VGAA-TFETs using InAs/Si Heterojunction on SOI substrate

Introduction Miniaturization of field-effect transistors (FETs) have serious issues in enhanced leakage current, short-channel effect, and power consumption. In this regard, the vertical gate all-around (VGAA) structure using the III-V compound semiconductor nanowires (NWs) is expected as alternative transistor to solve the problems in leakage current and short channel effect. There is still challenge in decreasing power consumption of the FET because the reduction in subthreshold slope (SS) has physical limitation in thermionic carrier transport (SS = 60 mV/dec). Tunnel FETs (TFETs) can lower the SS less than the physical limitation in MOSFETs and are expected to be used as next-generation low-voltage switching devices. We have demonstrated vertical gate-all-around (VGAA) TFET using III-V/Si tunnel junction which was formed by the selective-area growth of III-V NWs on Si and achieved a steep SS characteristics and complementary operation [1]. These demonstrations should be expanded on silicon-on-insulator (SOI)(111) platforms toward circuit applications using the III-V/Si VGAA-TFETs. Here, selective-area growth of the InAs NWs on thin SOI(111) substrates and demonstrated InAs/Si VGAA-TFETs on SOI platforms.Experimental procedureFirst, a 35-nm-thick SiO2 film was formed on p-type SOI(111) by thermal oxidation. The SOI thickness was 600 nm. Periodical circular openings were formed using electron beam lithography and dry/wet etchings. Next, InAs NWs were grown by selective-area growth. Here, we used a pulse growth technique to orient NWs in the vertical <111>B direction on a nonpolar SOI substrate, making the substrate surface polar (111)B, and aligning vertical NWs [2]. Next, we fabricated VGAA-TFETs by using three-dimensional device process in previous reports [1]. First, Hf0.8Al0.2O were formed as gate oxides by atomic layer deposition (ALD). Next, 200 nm-thick tungsten (W) was deposited around the NW sidewalls as gate metal. After that source metal (Ti/Au) was evaporated 20 nm/50 nm on the substrate by EB vapor deposition. Next, benzocyclobutene (BCB) was used as isolation layer between gate and drain metals. Then drain metal (Ti/Pd/Au) was evaporated 20 nm/20 nm/50nm on the top of the NWs. Finally, the VGAA-TFETs were annealed at 350 - 400°C in order in N2 for ohmic contacts in the source and drain regions. VGAA-TFETs were measured after annealing for each temperature.ResultsThe growth results showed vertical InAs NWs were successfully integrated on the p-SOI(111) substrates. The grown InAs NWs have hexagonal pillar structures surrounded with {-110} vertical facets and (111) B planes. Each NWs were composed of axial Zn-pulse doped intrinsic/Si-doped n-type/Sn-pulse doped n+-type NW segments. The average height is inversely proportional to the square of the diameter. Therefore, as similar to the conventional selective growth of InAs NWs on Si(111), the surface diffusion process of In atoms was dominant for the NW growth on SOI(111) surface.Transfer characteristics of the fabricated VGAA-TFET after annealed at 350°C indicated the tunnel current in the InAs/Si tunnel junction was electrically modulated by gate bias. The minimum SS was 37 mV/dec at VDS = 0.50 V, which was less than the theoretical limitation of conventional MOSFETs.The on-state current was 21 nA/μm at drain and source (VDS) of 1.00 V. The off current was 6.5 fA/μm when VDS was 1.00 V. Also, the threshold voltage (VTH) was 0.55 V. Transconductance was 31 nS/μm at VDS = 0.50 V. The measured current and transconductance were normalized by the number of NWs and the gate outer perimeter.We also investigated anneal temperature dependence of the device performance. The increasing in anneal temperature slightly lowered the minimum SS from 37 mV/dec to 23 mV/dec. And the on-state current was increased with increasing the anneal temperature. However, nonlinearity in the output IDS – VDS curve was enhanced with increasing the anneal temperature. This was assumed to be formed Schottky contact on the source metal. At the higher anneal temperature above 380°C, Ti/Au source metal possibly formed silicide (TiSi2) layer at the Ti/p-SOI interface. Thus, the contact resistance was decreased by the silicidation, and the on-state current was increased. However, Schottky contact of Au/Si was partially formed through the silicidation layer due to the very thin Ti interlayer. One of the possible approaches was to increase the Ti thickness or to use Al or Cu as single layer film. Further improvement of the device performance will be discussed.[1] K.Tomioka et al., IEEE IEDM. Tech. Dig. (2020) 429-432[2] K.Tomioka et al., Nano Lett. 8(2008) 3475-3480

Selective-Area Growth of InGaAs Nanowires on SOI and the Vertical Transistor Application

INTRODUCTIONConventional field-effect transistors (FETs) are expected to have new gate structures and channel materials to avoid serious issues caused by the miniaturization of FETs, such as enhanced leakage currents and short-channel effects. With this regard, III-V compound semiconductor nanowires (NWs) have attracted much attention as one of the alternative channel materials because of their fast carrier mobility and compatibility with the gate-all-around (GAA) structure. We have demonstrated vertical GAA (VGAA) field-effect transistors (FETs) using InGaAs NWs on Si [1]. For circuit applications, this demonstration must be expanded on silicon-on-insulator (SOI) platforms. Here, we demonstrated the selective growth of vertical InGaAs NWs on SOI (111) and InGaAs VGAA-FETs on SOI (111).EXPERIMENTSThe InGaAs nanowires (NWs) were grown on n-type silicon-on-insulator (SOI) substrates by the selective-area epitaxy. The SOI layer had a thickness of 600 nm. First, a 15-nm-thick SiO2 film was formed on SOI (111) by thermal oxidation. Next, we formed circular mask openings using electron beam lithography, reactive ion etching (RIE), and wet etching. Then, after the formation of (111) B-polar surface [2], we grew InGaAs NWs by metal-organic vapor phase epitaxy (MOVPE). Trimethylgallium (TMGa), trimethylindium (TMIn), and arsine (AsH3) were used as precursor materials. In addition, silane (SiH4), diethylzinc (DEZn), and tetraethyltin (TESn) were used as n-type and p-type dopants.Next, we fabricated VGAA-FETs. At first, we deposited a 10-nm-thick Hf0.8Al0.2O gate oxide film using atomic layer deposition (ALD). Next, we deposited a 200-nm-thick tungsten (W) film for the gate electrode by sputtering. Then, we covered the NWs with benzocyclobutene (BCB) by spin coating and etched the BCB, W, and Hf0.8Al0.2O, and top of the NWs, simultaneously. We repeated the BCB coating and the etching process to isolate the gate and drain electrodes. Then, we formed a drain electrode (Ti/Pd/Au) on top of the NWs, and a source electrode (Ni/Au) on the n-SOI surface by evaporation. Finally, to obtain an ohmic contact between the electrode and the NW, we annealed the devices at 420°C in N2.RESULTSThe InGaAs NWs were vertically aligned on n-type SOI (111) substrates by the selective-area epitaxy, indicating (111) B-oriented surface was formed on SOI (111). The average diameter of the NW was 70 nm, and the average height was 2000 nm. The NWs had axial segments: Zn pulse-compensated intrinsic segment, Si-doped n-type segment, and Sn pulse-doped n-type segment. The segment heights were 800 nm, 240 nm, and 960 nm, respectively.The VGAA-FETs using the InGaAs NWs on an SOI substrate exhibited moderate switching characteristics. The VGAA-FETs had a threshold voltage (VTH) of 1.0 V and a subthreshold slope (SS) of 178 mV/dec. The on-off current ratio was 104 and the on-state drain current (Ids) was 7.6×10-4 μA/μm at the drain-source voltage (VDS) of 0.5 V. The transconductance (gm) was 2.0×10-3 μS/μm and the gate leakage current was approximately 9.5×10-3 pA/μm at VDS of 0.5V.The SS was slightly higher than the minimum SS at room temperature (60 mV/dec). This was caused by a high off-leakage current. The high off-leakage current originated from the quality of the oxide/NW interface and the gate-induced barrier lowering.In the output characteristics, the linear region exhibited a nonlinear curve. This was because Schottky contact was formed between the Ni/Au and the Si interface due to the thin Ni layer. The output characteristics indicated that the off-state leakage current was also modulated by negative VGS. This was because the SOI layer was electrically floated due to the above incomplete Ohmic contact and may have been modulated by the gate voltage. In the conference, the details of the selective area growth method of vertical InGaAs NWs and the improvements in the VGAA-FETs properties will be discussed.[1]. K. Tomioka et al., Nature 488 (2012) 189.[2]. K. Tomioka et al., IEEE J. Selec. Top. Quant. Elec. 17 (2019) 1112.

The Influence of Nickel Doping on the Metal-Oxide in Solution-Processed Transistors Based on Indium Zinc Oxide

Solution-processing of nickel zinc oxide (IZO) thin-film transistors (TFTs) is gaining traction as a cornerstone of future display technology, promising cost-effective production. However, achieving stability in the off-current state of IZO without using Ga, a less eco-friendly dopant, remains a challenge. This study proposes a solution-based doping method for IZO semiconductors employing a Ni carrier suppressor and examines the impact of Ni on transistor operation. By leveraging the similar size of Ni2+ to Zn2+, an optimal Ni concentration selectively substitutes Zn sites, leading to a reduction in hydroxide groups bonded to Zn and enhancing the bonding strength of Ni with O. Conversely, excessive Ni addition impedes the formation of a smooth thin film. Ni-doped IZO TFT devices with optimized Ni concentrations exhibit superior performance, characterized by significantly lower off-state currents while maintaining high on-state currents compared to conventional IZO TFTs. This approach expands the repertoire of solution-processed metal oxide semiconductors, offering a sustainable alternative for carrier suppression and facilitating the cost-effective and straightforward fabrication of TFTs.

Fully coupled electron-phonon transport in two-dimensional-material-based devices using efficient FFT-based self-energy calculations

Self-heating can significantly degrade the performance in silicon nanoscale devices. In this work, the impact of self-heating is investigated in nanosheet transistors made of two-dimensional materials using ab-initio techniques. A new algorithm was developed to allow for efficient self-energy computations, achieving a ∼500 times speedup. It is found that for the simple case of free-standing transition-metal dicalchogenides without explicit metal leads, electron-phonon scattering with room-temperature phonons dominates the device performance. For MoS2, the effect of self-heating is negligible in comparison. For WS2 and especially for WSe2, self-heating effects demonstrate a further degradation of the ON-state current.

Ultra-sensitive dengue NS1 protein detection via asymmetric source-drain, heterojunction and dual-dielectric cavities in a uniform tunnel FET biosensor

In this paper, we present a unique Asymmetric Source-Drain Heterojunction Dual-Dielectric Uniform Tunnel Field Effect Transistor (A-SD-HJ-DD-UTFET) based biosensor tailored for the early detection of dengue NS1 protein during the acute phase of infection offering early diagnosis and potentially life-saving intervention. The proposed biosensor design features simplified fabrication, a narrow drain region, and a dual material control gate, enhancing specificity and sensitivity for dengue virus detection. Using a heterojunction configuration, this device optimizes electron flow for improved detection accuracy. The roles of Tunnel Gate (TG) and Auxiliary Gate (AG) are studied in terms of band energy, electric field, electrostatic potential, and other sensitivity parameters. Sentaurus TCAD tool is utilized for analyzing the characteristics of the proposed A-SD-HJ-DD-UTFET biosensor. Simulation results indicate that the designed A-SD-HJ-DD-UTFET biosensor achieves a superior Subthreshold Swing (SS) of 15.4 mV/dec and an enhanced ION/IOFF sensitivity of about 2.25 × 10¹¹ with a maximum ON and minimum OFF state currents of 2.28 × 10–4 A/μm and 1.28 × 10–16 A/μm respectively for detecting NS1 protein of dengue. Additionally, it boasts a high switch ratio in the order of 1012. The proposed biosensor outperforms conventional devices, including the state-of-the-art Junctionless (JL)-TFET biosensors. The superior electrical characteristics of the proposed A-SD-HJ-DD-UTFET biosensor make it a promising device for early detection of the dengue NS1 protein, providing a potent solution for mitigating the spread of dengue infections.

First demonstration of a self-aligned p-channel GaN back gate injection transistor

In this study, we present the development of self-aligned p-channel GaN back gate injection transistors (SA-BGITs) that exhibit a high ON-state current. This achievement is primarily attributed to the conductivity modulation effect of the 2-D electron gas (2DEG, the back gate) beneath the 2-D hole gas (2DHG) channel. SA-BGITs with a gate length of 1 μm have achieved an impressive peak drain current (I D,MAX) of 9.9 mA/mm. The fabricated SA-BGITs also possess a threshold voltage of 0.15 V, an exceptionally minimal threshold hysteresis of 0.2 V, a high switching ratio of 107, and a reduced ON-resistance (R ON) of 548 Ω·mm. Additionally, the SA-BGITs exhibit a steep sub-threshold swing (SS) of 173 mV/dec, further highlighting their suitability for integration into GaN logic circuits.

Evaluating the performance of triple and double metal gate charge plasma transistors for applications in biological sensors at a dual cavity location

BackgroundBiosensors have become essential tools in biotechnology, environmental monitoring, and healthcare industries due to their ability to detect and analyze biological signals. However, conventional Tunnel Field-Effect Transistors (TFETs) used in biosensors face challenges like reduced ON-state current, random dopant fluctuations, and complex manufacturing processes, which limit their effectiveness. AimThe study aims to investigate the effectiveness of Charge Plasma-based Tunnel Field-Effect Transistors (CP-TFETs) with dual and triple metal gate-dual cavity locations for improving the sensitivity and performance of biosensors. MethodologyThe study compares dual and triple metal gate CP-TFET configurations for signal amplification and detection in biosensors. The CP-TFETs use high-k gate dielectric materials to enhance ON-state current and reduce OFF-state current, while the impact of neutralized and charged substances in the cavities on surface energy, electric field, and energy bands is analyzed. ResultsThe triple metal gate configuration demonstrated superior sensitivity in detecting biomolecules compared to the dual metal gate. By utilizing high-k materials and optimizing the gate work function, the triple metal gate approach achieved higher drain current and reduced OFF-state current, leading to improved overall performance. ConclusionThe triple metal gate CP-TFET outperforms its dual metal counterpart in biosensor applications, offering higher sensitivity, increased ON-state current, and improved detection capabilities, making it a promising approach for enhancing biosensor effectiveness.

Properties Investigation and Damage Analysis of GaN Photoconductive Semiconductor Switch Based on SiC Substrate.

The GaN photoconductive semiconductor switches (PCSSs) with low leakage current and large on-state current are suitable for several applications, including fast switching and high-power electromagnetic pulse equipment. This paper demonstrates a high-power GaN lateral PCSS device. An output peak current of 142.2 A is reached with an input voltage of 10.28 kV when the GaN lateral PCSS is intrinsically triggered. In addition, the method of retaining the AlGaN/GaN heterostructure between electrodes on PCSSs is proposed, which results in increasing the output peak current of the PCSS. The damage mechanism of the PCSS caused by a high electric field and high excitation laser energy is analyzed. The obtained results show that the high heat generated by the large current leads to the decomposition of GaN, and thus, the Ga forms a metal conductive path, resulting in the failure of the device.

Heterostructure WSe2/copper hexadecafluorophthalocyanine (F16CuPc) field-effect transistors for efficient suppression of electron transport

The use of the organic semiconductor copper hexadecafluorophthalocyanine (F16CuPc) in WSe2 based heterostructure field-effect transistors (FETs) is shown to result in a large reduction in electron current while not significantly impacting the hole current. This approach is promising for use in p-channel FETs in which electron transport is undesirable and increases leakage currents and power dissipation in the off-state. The reduction in on-state electron currents, by up to three orders of magnitude, is due to the transfer of electrons to the low-mobility states in F16CuPc due to the greater electron affinity of the organic semiconductor compared to WSe2. The off-state currents under a drain bias are reduced by more than four orders of magnitude due to the effective suppression of electron currents. This is a result of the formation of type II heterostructure between F16CuPc and WSe2. Electrons in this heterostructure FET will preferentially transfer to F16CuPc, while holes will tend to remain in the high mobility WSe2 layer. This effect is more marked in monolayer WSe2 based FETs compared to multilayer WSe2 FETs due to a larger difference in electron affinities with respect to F16CuPc. Also, the magnitude of electron current suppression was further enhanced when F16CuPc is deposited only on a part of the channel near the source of WSe2 +F16CuPc FETs.

High-performance single-crystalline In2O3 field effect transistor toward three-dimensional large-scale integration circuits

Formation of a single crystalline oxide semiconductor on an insulating film as a channel material capable of three-dimensional (3D) stacking would enable 3D very-large-scale integration circuits. This study presents a technique for forming single-crystalline In2O3 having no grain boundaries in a channel formation region on an insulating film using the (001) plane of c-axis-aligned crystalline indium gallium zinc oxide as a seed. Vertical field-effect transistors using the single-crystalline In2O3 had an off-state current of 10−21 A μm−1 and electrical characteristics were improved compared with those using non-single-crystalline In2O3: the subthreshold slope was improved from 95.7 to 86.7 mV dec.−1, the threshold voltage showing normally-off characteristics (0.10 V) was obtained, the threshold voltage standard deviation was improved from 0.11 to 0.05 V, the on-state current was improved from 22.5 to 28.8 μA, and a 17-digit on/off ratio was obtained at 27 °C.

Enhancing phase and morphology control of vanadium oxide films for resistive memory applications: A water-assisted chemical approach

This study explores the influence of precursor solution composition and solvent selection on the synthesis of vanadium oxide (VO2) thin films tailored for resistive memory applications. The vanadium pentoxide and oxalic acid molar ratio and the dispersing medium (ethanol, water, and their mixture) were varied. Water content significantly influenced the VO2 phase, morphology, and film thickness. Ethanol yielded mixed vanadium oxide phases VO2 − Tetragonal, V2O5 − Orthorhombic, and Monoclinic) and a film with minor imperfections. Conversely, the active layer prepared using an aqueous medium showed a predominant VO2 − Monoclinic phase, albeit with a non-uniform film. An ethanol–water mixture produced the most uniform morphology and a mixture of vanadium oxide phases (VO2 − Tetragonal, V2O5- Orthorhombic). All devices displayed resistive switching behavior. VO2-containing devices exhibited a more pronounced transition from an ohmic conduction state to a space-charge-limited conduction mechanism. ON-state currents remained consistent, while OFF-state currents varied notably.

GaAs-on-insulator based vertical heterojunction tunnel FET: proposal and analysis for VLSI circuit applications

This work analyses the Gallium Arsenide (GaAs)-on-insulator based vertical heterojunction tunnel FET with Gallium Antimonide (GaSb) as source material and GaAs as channel/drain material (GaSb/GaAs VTFET) to enhance the performance of the device and is compared with the Silicon-based VTFET. Silvaco Atlas TCAD tool is employed to perform numerical calculations. Tentative fabrication process flow of GaSb/GaAs VTFET is presented. GaSb is a low bandgap material that enhances the tunneling of charge carriers at source-channel heterojunction. GaSb/GaAs VTFET device outperforms Si-based VTFET in terms of electrical performance metrics such as ON-state current (ION), and ION/IOFF increases by a factor of 11 and 270 respectively; whereas OFF-state current (IOFF), subthreshold swing (SS), threshold voltage (VT) and drain-induced barrier lowering (DIBL) reduce by 95.98%, 39.36%, 17.14% and 29.17% respectively. Further, analog/RF and linearity/distortion performance analysis is carried out. GaSb/GaAs VTFET has improved analog/RF performances in terms of cut-off frequency (fT), gain-bandwidth product (GBP), transit time (τ), device efficiency (DE), transconductance frequency product (TFP) and suppressed distortions in compare to Si-based VTFET. Finally, GaSb/GaAs VTFET is evaluated for process variations and designing digital inverter and common source amplifier circuits. The Look-up-table (LUT) based Verilog-A model within the CADENCE tool has been employed to scrutinize the transient responses of inverter and common source amplifier circuits. Unity gain frequency and 3-dB bandwidth obtained for GaSb/GaAs VTFET amplifier are 15 GHz and 5.97 GHz. Therefore, this work presents GaSb/GaAs VTFET’s strong candidature for analog and digital VLSI circuit designing.

Simulations of Anisotropic Monolayer GaSCl for p-Type Sub-10 nm High-Performance and Low-Power FETs.

Two-dimensional materials have been extensively studied in field-effect transistors (FETs). However, the performance of p-type FETs has lagged behind that of n-type, which limits the development of complementary logical circuits. Here, we investigate the electronic properties and transport performance of anisotropic monolayer GaSCl for p-type FETs through first-principles calculations. The anisotropic electronic properties of monolayer GaSCl result in excellent device performance. The p-type GaSCl FETs with 10 nm channel length have an on-state current of 2351 μA/μm for high-performance (HP) devices along the y direction and an on-state current of 992 μA/μm with an on/off ratio exceeding 107 for low-power (LP) applications along the x direction. In addition, the delay-time (τ) and power dissipation product of GaSCl FETs can fully meet the International Technology Roadmap for Semiconductors standards for HP and LP applications. Our work illustrates that monolayer GaSCl is a competitive p-type channel for next-generation devices.

Ballistic 2D MoS2 transistors with ultra-high on-state currents

Ballistic 2D MoS2 transistors with ultra-high on-state currents

Inner Doping of Carbon Nanotubes with Perovskites for Ultralow Power Transistors.

Semiconducting carbon nanotubes (CNTs) are considered as the most promising channel material to construct ultrascaled field-effect transistors, but the perfect sp2 C─C structure makes stable doping difficult, which limits the electrical designability of CNT devices. Here, an inner doping method is developed by filling CNTs with 1D halide perovskites to form a coaxial heterojunction, which enables a stable n-type field-effect transistor for constructing complementary metal-oxide-semiconductor electronics. Most importantly, a quasi-broken-gap (BG) heterojunction tunnel field-effect transistor (TFET) is first demonstrated based on an individual partial-filling CsPbBr3/CNT and exhibits a subthreshold swing of 35mV dec-1 with a high on-state current of up to 4.9µA per tube and an on/off current ratio of up to 105 at room temperature. The quasi-BG TFET based on the CsPbBr3/CNT coaxial heterojunction paves the way for constructing high-performance and ultralow power consumption integrated circuits.

Mobility and current boosting of In-Ga-Zn-O thin-film transistors with metal capping layer oxidation

This study investigates the effect of an oxidized Ta capping layer on the boosting of field-effect mobility (μ FE) of amorphous In-Ga-Zn-O (a-IGZO) Thin-film transistors (TFTs). The oxidation of Ta creates additional oxygen vacancies on the a–IGZO channel surface, leading to increased carrier density. We investigate the effect of increasing Ta coverage on threshold voltage (V th), on-state current, μ FE and gate bias stress stability of a-IGZO TFTs. A significant increase in μ FE of over 8 fold, from 16 cm2 Vs−1 to 140 cm2 Vs−1, was demonstrated with the Ta capping layer covering 90% of the channel surface. By partial leaving the a-IGZO uncovered at the contact region, a potential barrier region was created, maintaining the low off-state current and keeping the threshold voltage near 0 V, while the capped region operated as a carrier-boosted region, enhancing channel conduction. The results reported in this study present a novel methodology for realizing high-performance oxide semiconductor devices. The demonstrated approach holds promise for a wide range of next-generation device applications, offering new avenues for advancement in metal oxide semiconductor TFTs.

Performance optimization of AlGaAs and Al x Ga 1−x As based SM-TM-DG-JL-TFET for an analog/RF applications

This study aims to enhance the efficiency of the Double Gate-Junctionless-Tunnel Field Effect Transistor (DG-JL-TFET) by optimizing the utilization of AlGaAs and GaAs/Si/AlGaAs-based Single Material and Tri-Material (SM and TM) configurations.In order to overcome the drawbacks of present TFET architectures, such as their limited ability to drive current and their ambipolar behaviour, and to enhance the on-state current, To execute our suggested SM-TM-DG-JL-TFET configuration. The TM structure exhibits a greater on-state current (I on ) and a lower SubthersholdSwing (SS) in comparison to SM structures. This study quantifies the Unit-gain-current-cut-off-frequency (f t ) and Maximum oscillation frequency fmax by manipulating geometric parameters such as gate length(l g ), gate-oxide thickness, and Channel thickness. The TM structure exhibits a significantly greater on-state current (I on ) of 14 × 10−3 A. Compared to SM structures, while simultaneously reducing the off-state current (I off ), subthreshold swing (SS), and threshold voltage (V t ). TM structures exhibit higher values of f t and fmax in DG-JL-TFET due to their enhanced output conductance compared to SM structures. The device exhibits potential for future low-power-RF applications due to its significant values of f t and fmax .