On-chip Process Research Articles

On-chip PMA labeling of foodborne pathogenic bacteria for viable qPCR and qLAMP detection

Propidium monoazide (PMA) is a membrane impermeable molecule that covalently bonds to double stranded DNA when exposed to light and inhibits the polymerase activity, thus enabling DNA amplification detection protocols that discriminate between viable and non-viable entities. Here, we present a microfluidic device for inexpensive, fast, and simple PMA labeling for viable qPCR and qLAMP assays. The three labeling stages of mixing, incubation, and cross-linking are completed within a microfluidic device that is designed with Tesla structures for passive microfluidic mixing, bubble trappers to improve flow uniformity, and a blue LED to cross-link the molecules. Our results show that the on-chip PMA labeling is equivalent to the standard manual protocols and prevents the replication of DNA from non-viable cells in amplification assays. However, the on-chip process is faster and simpler (30 min of hands-off work), has a reduced likelihood of false negatives, and it is less expensive because it only uses 1/20th of the reagents normally consumed in standard bench protocols. We used our microfluidic device to perform viable qPCR and qLAMP for the detection of S. typhi and E. coli O157. With this device, we are able to specifically detect viable bacteria, with a limit of detection of 7.6 × 103 and 1.1 × 103 CFU/mL for S. typhi and E. coli O157, respectively, while eliminating amplification from non-viable cells. Furthermore, we studied the effects of greater flow rates to expedite the labeling process and identified a maximum flow rate of 0.7 μL/min for complete labeling with the current design.

Bitcell-Based Design of On-Chip Process Variability Monitors for Sub-28 nm Memories

On-chip process monitor/sensor circuits capture the process corner of a chip in the postfabrication stage. Logic-NMOS and logic-PMOS based sensors, however, fail to capture the process corners for memories, as bitcells have a different implant from logic cells. In this paper, a novel on-chip bitcell-based process monitor (BPMON) circuit is implemented that distinguishes between and detects the standard global corner of memories in any chip. It leverages a current-mirror and a near-threshold biased bitcell array structure that changes the output voltage of the circuit in accordance with changes in the process corner. BPMON separately tracks bitcell NMOS and bitcell PMOS process corners. Silicon data from over 100 chips from five wafers in 28 nm CMOS shows correct bitcell process corner predictions. These predictions show the expected strong correlation with read and write vccmin, enabling vccmin to be lowered below specifications while still achieving a 100% yield.

A Laminated Microfluidic Device for Comprehensive Preclinical Testing in the Drug ADME Process.

New techniques are urgently needed to replace conventional long and costly pre-clinical testing in the new drug administration process. In this study, a laminated microfluidic device was fabricated to mimic the drug ADME response test in vivo. This proposed device was loaded and cultured with functional cells for drug response investigation and organ tissues that are involved in ADME testing. The drug was introduced from the top of the device and first absorbed by the Caco-2 cell layer, and then metabolized by the primary hepatocyte layer. It subsequently interacted with the MCF-7 cell layer, distributed in the lung, heart and fat tissues, and was finally eliminated through the dialysis membrane. Throughout this on-chip ADME process, the proposed device can be used as a reliable tool to simultaneously evaluate the drug anti-tumor activity, hepatotoxicity and pharmacokinetics. Furthermore, this device was proven to be able to reflect the hepatic metabolism of a drug, drug distribution in the target tissues, and the administration method of a drug. Furthermore, this microdevice is expected to reduce the number of drug candidates and accelerate the pre-clinical testing process subject to animal testing upon adaptation in new drug discovery.

A Microfluidic Device with Integrated Sonication and Immunoprecipitation for Sensitive Epigenetic Assays

Epigenetic studies increasingly require analysis of a small number of cells that are of one specific type and derived from patients or animals. In this report, we demonstrate a simple microfluidic device that integrates sonication and immunoprecipitation (IP) for epigenetic assays, such as chromatin immunoprecipitation (ChIP) and methylated DNA immunoprecipitation (MeDIP). By incorporating an ultrasonic transducer with a microfluidic chamber, we implemented microscale sonication for both shearing chromatin/DNA and mixing/washing of IP beads. Such integration allowed highly sensitive tests starting with 100 cross-linked cells for ChIP or 500 pg of genomic DNA for MeDIP (compared to 106–107 cells for ChIP and 1–10 μg of DNA for MeDIP in conventional assays). The entire on-chip process of sonication and IP took only 1 h. Our tool will be useful for highly sensitive epigenetic studies based on a small quantity of sample.

All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator

In this paper, an all-digital ON-chip process sensor using a ratioed inverter-based ring oscillator is proposed. Two types of the ratioed inverter-based ring oscillators, nMOS and pMOS types, are proposed to sense process variation. The nMOS (pMOS)-type ring oscillator is designed to improve its sensitivity to the process variation in the nMOS (pMOS) transistors using the ratioed inverter that consists of only nMOS (pMOS) transistors. A compact process sensor can be realized using only these two types of ring oscillators. For a suitable ON-chip implementation, the output of the proposed process sensor is provided with a digital code. The proposed process sensor is fabricated using a 0.13- $\mu \text{m}$ CMOS technology. Measurement results from 30 fabricated chips show that all chips have the same process corner. To verify whether the proposed sensor can properly sense all the process corners, the threshold voltage of the fabricated chips is shifted by body biasing. The verification results show that the measured code error compared with the postlayout simulation is less than 2.92%.

Nanohole Array-Directed Trapping of Mammalian Mitochondria Enabling Single Organelle Analysis.

We present periodic nanohole arrays fabricated in free-standing metal-coated nitride films as a platform for trapping and analyzing single organelles. When a microliter-scale droplet containing mitochondria is dispensed above the nanohole array, the combination of evaporation and capillary flow directs individual mitochondria to the nanoholes. Mammalian mitochondria arrays were rapidly formed on chip using this technique without any surface modification steps, microfluidic interconnects, or external power sources. The trapped mitochondria were depolarized on chip using an ionophore with results showing that the organelle viability and behavior were preserved during the on-chip assembly process. Fluorescence signal related to mitochondrial membrane potential was obtained from single mitochondria trapped in individual nanoholes revealing statistical differences between the behavior of polarized vs depolarized mammalian mitochondria. This technique provides a fast and stable route for droplet-based directed localization of organelles-on-a-chip with minimal limitations and complexity, as well as promotes integration with other optical or electrochemical detection techniques.

On-chip aqueous two-phase system (ATPS) formation, consequential self-mixing, and their influence on drop-to-drop aqueous two-phase extraction kinetics

Aqueous two-phase systems (ATPSs) allow an advantageous aqueous two-phase extraction process (ATPE), a special type of liquid–liquid extraction. Compared with conventional liquid–liquid extraction using aqueous/organic extraction media, ATPE is known to provide relatively easy mass transfer and a gentle environment for biological separation applications. Considering the recent interest in microscale ATPE, we aimed to study (i) the potential of preparing ATPS droplets on a digital microfluidic device, and (ii) the influence of the fluidic dynamics created during the formation of ATPS, with the goal of enhancing on-chip ATPE process. On-chip ATPS formation was evaluated by preparing a series of ATPSs on electrowetting on dielectric digital microfluidic chips and comparing their characteristics with the same ATPSs prepared at macroscale using conventional procedures. An enhanced on-chip drop-to-drop ATPE process was achieved by incorporating a self-mixing condition created during ATPSformation. Results indicate a successful on-chip ATPS preparation as well as enhanced extraction performance by self-mixing in the absence of forced mixing. Findings of this research suggest an alternative, simple, yet adequate technique to provide mixing for on-chip applications, such as sample preparation in portable microfluidics, for which it is unfavorable to implement complicated mixing sequences or complex device geometries.

Reconfigurable Adaptive Routing Buffer Design for Scalable Power Efficient Network On Chip

The layout density of integrated circuits on a single chip has led to the reduced size at sub-micron scales of VLSI design. The System on Chip (SOC) design has few challenges, such as latency, power, area and reliable data transmission among sub-systems interconnected on a single chip. Network on Chip (NOC) is a subset of SOC which accomplishes on-chip communication process. The performance of NOC architecture is significantly affected by power and area. This research work has focused on a new low power reconfigurable NOC architecture with repeaters between the routers. The repeater enables zero buffers between the interlink routers. It works on the principles of store and forward process. The proposed architecture is implemented using mesh network topology. The simulated results of new architecture have shown a reduction in power dissipation by 56% and reduction in on chip area by as much as 60%. Keywords: Network on Chip (NOC), Reconfigurable Architecture, System on Chip (SOC)

Effect of a microwave warming of cell culture media on cell viability and confluence rate

Here we present a method for rapidly and stably warming up a small volume of cell culture media that can maintain cell viability and confluence rate. This method uses microwave radiation for warming without any direct contact with water, preventing the potential issue of contamination induced by the use of a water bath. To demonstrate the proof of concept validation, we used a conventional microwave oven for warming cell culture media. In our experiments, it took only 10 s to warm a 50 mL-media tube (mostly proper volume for the use of microfluidic cell culture experiments) up to 37 °C. Multiple tubes can also be used to increase the volume of cell culture media by placing them in a plastic support within the oven at the same time in a scalable manner. The results show that there was no jump discontinuity to a higher temperature than 37 °C within 10 s. Both apoptosis and necrosis were monitored and examined to confirm whether the new method can affect cell viability and metabolism. The proposed method is fast, easy and user-friendly in conventional cell culture process, even scalable for the use of large media volume, and free of biological contamination due to water contact occurred by use of conventional water baths. We furthermore believe that this approach can be potentially helpful for advancing on-chip cell culture process that may require a small volume of cell culture media often used in microfluidic devices.

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores

This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application processor (AP). This AP has a combination of high-performance 2 GHz cores and energy-efficient 1 GHz cores. The maximum performance in the octa-core configuration is 35,600 DMIPS. The key design highlights are as follows. 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2 GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28 nm HPM process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg), resulting in 24% leakage reduction of L1 cache. 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 20% dynamic power reduction, 29% leakage power reduction and 40 mV improvement of minimum operation voltage are achieved. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC voltage drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.

Pipelined hardware design of self tuning controller with on-chip parameter estimator

This paper intends to propose a pipelined design of floating point-based self tuning controller STC with on-chip process parameter estimator using recursive least square RLS algorithm used for real time control applications. The parameter estimation algorithm runs continuously to allow the model of the system to be updated at each sample interval as changes occur in the process and the algorithm estimates the unknown process parameters recursively based on the minimisation of the least squares error. The estimated parameters are validated with actual parameters of first and second discrete single input single output SISO linear processes. The proposed pipelined design of STC is analysed with the second order process. The process is controlled by RST controller and its parameters are identified with minimum degree pole placement technique. The design is implemented in very high-speed integrated circuit hardware description language VHDL and is tested using Virtex IV device 4VLX200ff1513. The maximum operating frequency of pipelined design of STC is 146.735 MHz.

Process, voltage and temperature compensation in a 1-MHz 130nm CMOS monolithic clock oscillator with 2.3% accuracy

This paper presents an on-chip process, voltage and temperature (PVT) compensation technique for a 1-MHz monolithic clock oscillator in a CMOS process. The oscillator is based on carrier mobility and frequency-to-voltage converter (FVC), which is based on charge pump circuit. An adaptive charge current maintains a constant frequency without trimming. Furthermore, a reference voltage with a second-order temperature coefficient further compensates the variation of frequency with temperature. It improves the accuracy of existing carrier-mobility-based oscillator, from 4.5% to 2.3%. The circuit was designed in a 130 nm CMOS 3.3 V device process. The results show that the output frequency is within 2.3% variation in the worst case. The variations of frequency with process, temperature (−40 to 125°C) and power supply are within 1.8%, 0.8% and 0.2%/V, respectively. It achieves a CMOS monolithic clock oscillator insensitive to PVT.

An on-chip Cell-SELEX process for automatic selection of high-affinity aptamers specific to different histologically classified ovarian cancer cells.

Ovarian cancer (OvCa) is the second most common type of gynecological cancer. More seriously, the prognosis for survival is relatively poor if an early OvCa diagnosis is not achieved. However, it is extremely challenging to diagnose very early stage OvCa, when treatments are the most effective, because of the lack of specific and sensitive biomarkers. Therefore, in order to achieve early detection of OvCa, screening and identifying biomarkers with high specificity and affinity are greatly needed. In this study, an integrated microfluidic system capable of performing cell-based systematic evolution of ligands by an exponential enrichment (Cell-SELEX) process was developed for automatic, high-throughput screening of multiple cell lines to competitively select aptamer-based biomarkers for OvCa. This on-chip Cell-SELEX process only required five rounds of aptamer selection, which is much faster than using a conventional SELEX process (22 rounds). Using this on-chip process, 13 aptamers specific to OvCa cells were successfully screened and three of them showed high affinity towards target cells with dissociation constants of 1.8 nM, 8.3 nM, and 1.3 nM. Analysis of stained fluorescence images and competitive testing against multiple cancer cell lines (cervical cancer, breast cancer, lung cancer, and liver cancer) were performed to verify the specificity of these selected aptamers. The results demonstrated that this developed system could perform the on-chip Cell-SELEX selection successfully and could be applied for personalized aptamer screening or targeted therapy monitoring in the near future.

Computational models in microfluidic bubble logic

The recent advancements in $$bubble\, logic$$ computation based on two-phase microfluidics bring into light the possibility that the use of bubbles in microfluidic devices can carry on-chip process control. In this paper, four computational models implementing two different AND–OR logic gates, one logic NOT, and a Flip-Flop are presented. More specifically, the numerical approach used combines the Navier–Stokes equation with the phase-field method. All reported models are based on generally accepted and already experimentally tested chip designs. A parametric T-junction model has been designed to be connected to the logic gate models as a droplet generator. The wider framework on the logic gate behavior in different operating conditions reveals the relevance of these models in the microfluidics chip design. Moreover, the advantage of using a simulation platform for the investigation of electrical circuits equivalent of microfluidic processes is illustrated. In this context, the focus of this paper was not only the definition of CFD models of logic gates, but the attempt to establish a workbench easily accessible for the study of the two-phase microfluidic processes.

Microfluidics-Assisted Diffusion Self-Assembly: Toward the Control of the Shape and Size of Pectin Hydrogel Microparticles

We demonstrated the generation of pectin hydrogel microparticles having complex shapes either by combining the phenomenon of gelation and water diffusion-induced self-assembly in microfluidic channels (on-chip) or by the deformation of the pregelled droplets outside the channels (off-chip) at a fluid-fluid interface. We proved that by tuning the mode of pectin cross-linking (CaCl2 vs CaCO3) and the degree of shrinking (water content in the dimethyl carbonate (DMC) organic continuous phase) we can control the shape of the final particle. Sphere, doughnut, oblate ellipsoid, or mushroom-type morphologies were thus produced, demonstrating the ability to control the formation of anisotropic biopolymer-based hydrogel microparticles using microfluidics. Shape changes were explained by the redistribution of calcium ions in combination with the local Peclet number experienced by the microdroplets during the on-chip process. Moreover, during the off-chip process, the interplay between elastic and viscous forces for microdroplets entering the CaCl2-DMC interface caused deformation of the pregelled droplets to occur and therefore resulted in the formation of microparticles with a mushroom-like morphology.

On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2$\,\times\,$VDD Output Buffers

A novel process and temperature compensation design for 2 VDD output buffers is proposed, where the threshold voltages (Vth) of PMOSs and NMOSs varying with process and temperature deviation could be detected, respectively. A prototype 2 × VDD output buffer using the proposed compensation design is fabricated using a typical 0.18 μm CMOS process. By adjusting output currents, the slew rate of output signals could be compensated over 117%. The maximum data rate with compensation is 120 MHz in contrast with 95 MHz without compensation, which is measured on silicon with an equivalent probe capacitive load of 10 pF.

On-chip growth of wafer-scale planar-type ZnO nanorod sensors for effective detection of CO gas

The facile engineering of sensing devices is an important technological achievement that will lead to large-scale and cost-effective fabrication of gas nanosensors. This study demonstrates the on-chip and selective growth process of zinc oxide (ZnO) nanorods (NRs) for wafer-scale fabrication of planar-type gas sensors using combined lithography and chemical hydrothermal techniques. This facile route can effectively fabricate ZnO NR gas sensors at low temperatures without the requirement of novel metal catalyst. The gas-sensing characteristics of the ZnO NR sensors to carbon monoxide (CO) and ammonia (NH3) were evaluated as a function of growth time in correlation with operating temperature and target gas concentration. The ZnO NR sensors showed good response and recovery characteristics with a maximum response to CO and NH3 gas at 400°C. The ZnO NR sensors grown at 6h exhibited the highest response to CO and NH3 gases with sensitivities of 0.37 and 0.05%/ppm, respectively. Furthermore, the gas-sensing mechanism of the ZnO NR sensors was also discussed in terms of three types NR/NR junctions, namely, point-junctions, across-junctions, and block-junctions.

Fabrication and characterization of tunable multiferroic Bi0.7Dy0.3FeO3 based on-chip micro-inductor

An optical lithographic process is developed to realize Si compatible on-chip micro-inductor using single phase room temperature multiferroic system like Bi0.7Dy0.3FeO3 (BDFO) as a core material. On-chip inductor is characterized for inductance and Q factor in the frequency range of 1kHz-1MHz. The properties are studied at different values of current passing through the coil and also bias applied directly across the BDFO core. Tunability goes on increasing with current and reaches as high as ~90% at 0.07A of DC current passing through the coil whereas ~30% tunability is obtained at 10V of DC voltage applied across the core. It indicates that substantial change in permeability occurs even at low fields due to presence of magnetoelectric (ME) coupling in BDFO system. The use of the single layer multiferroic BDFO core simplifies the on-chip fabrication process. In addition it helps to avoid the formation of defects that are normally formed at the interface of hetero-structures. Consequently it makes the process more reliable. The integration of the on-chip multiferroic micro-inductor would be useful in miniaturizing the inductive components in electronic device circuit.

A Highly Efficient On-chip 3D Plasmonic Nanofocusing Structure

ABSTRACTWe demonstrate and analyze a highly efficient on-chip 3D metal-insulator-metal (MIM) nanofocusing structure. Here, we show the in-depth theoretical design, analysis and discussion to provide a detailed picture of the highly efficient, on-chip nanofocusing process which is linearly tapered in 3D.

Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells

Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure.