Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells

Abstract

Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure.