On-chip Electrostatic Discharge Protection Research Articles

Ferroelectric Domain Wall Delayer and Low-Dropout Regulator.

A switching-type power converter providing an accurate and stable switching output voltage against line/load variations and power supply ripple is mostly complicated in system-on-chip power management integrated circuits (PMICs) within a limited occupation area. Here we fabricated domain wall (DW) nanodevices using an X-cut LiNbO3 thin film on silicon. The domain switching event occurs after a delay time predicted by Merz's law under the applied voltage. But the output current is irrespective of the applied voltage and can be adjusted by conducting wall width as well as input resistance in the circuit. The regulating currents appear repetitively across the volatile interfacial domains between the nanodevice and electrode under intermittently applied voltages. A wall-current-limited domain switching model is developed to explain the phenomenon. The multifunctional DW nanodevices with smaller occupation areas can serve as compact low-dropout regulators in PMICs, time-domain delayers in energy-efficient neural network systems, and on-chip electrostatic discharge protection besides nonvolatile memories and selectors.

Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit

Electrostatic discharge (ESD) and electromigration are critical issues that significantly impact the reliability of ICs. While both of these phenomena have been studied independently, the combination of the two, ESD-induced electromigration, has received less attention, potentially compromising IC reliability. This work analyzes various types of metal with different lengths, widths, and angles commonly used in ESD protection circuits in the CMOS process. The objective is to observe their behavior under continuous ESD zapping. The ESD-induced electromigration of metallization in the CMOS process has been analyzed, and metal sensitivity to system-level ESD events has also been identified. It is also analyzed from the perspective of energy that the ESD energy that metal can withstand will decrease as the ESD voltage increases, which will be even more detrimental to the ESD reliability of ICs. The findings from this study aim to provide valuable insights for designing metal lines in ICs to enhance ESD protection.

On-chip ESD Protection Design Methodologies by CAD Simulation

Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs) . On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional trial-and-error approaches become unacceptable to practical ESD protection designs for advanced ICs. Full-chip ESD protection circuit design optimization, prediction, and verification become essential to advanced chip designs, which highly depends on CAD algorithm and simulation that has been a constant research topic for decades. This paper reviews recent advances in CAD-enabled on-chip ESD protection circuit simulation design technologies and ESD-IC co-design methodologies. Key challenges of ESD CAD design practices are outlined. Practical ESD protection simulation design examples are discussed.

A novel robust SCR with high holding voltage for on-chip ESD protection of industry-level bus

In an industry-level bus, strong electrostatic interference seriously threatens the reliability of chips. However, the holding voltage (Vh) and robustness of traditional silicon-controlled rectifier (SCR) cannot meet the electrostatic discharge (ESD) window of industry-level applications. To better cope with extreme environments, this paper proposes a novel SCR with high robustness and latch-up immunity for on-chip ESD protection of the industry-level RS485 bus. By incorporating a surface current diverting path into the traditional SCR, the ESD characteristics of the proposed device are significantly improved. Through two-dimensional device simulation, the ESD characteristics of traditional SCR, proposed P-Well Floating SCR (PFSCR) and proposed P-Well Grounded SCR (PGSCR) are compared, with a focus on exploring the role of surface discharge path. Three types of SCR are realized based on the 0.18 μm BCD process. The transmission line pulse (TLP) test results show that PGSCR (13.64 V) has a higher Vh and higher robustness than traditional SCR (2.13 V) and PFSCR (4.39 V). In addition, the trigger voltage (Vt1:22.9 V) and failure current (It2:18.49A) of the PGSCR fully meet the ESD window of the target chip.

Graphene-Based ESD Protection for Future ICs.

On-chip electrostatic discharge (ESD) protection is required for all integrated circuits (ICs). Conventional on-chip ESD protection relies on in-Si PN junction-based device structures for ESD. However, such in-Si PN-based ESD protection solutions pose significant challenges related to ESD protection design overhead, including parasitic capacitance, leakage current, and noises, as well as large chip area consumption and difficulty in IC layout floor planning. The design overhead effects of ESD protection devices are becoming unacceptable to modern ICs as IC technologies continuously advance, which is an emerging design-for-reliability challenge for advanced ICs. In this paper, we review the concept development of disruptive graphene-based on-chip ESD protection comprising a novel graphene nanoelectromechanical system (gNEMS) ESD switch and graphene ESD interconnects. This review discusses the simulation, design, and measurements of the gNEMS ESD protection structures and graphene ESD protection interconnects. The review aims to inspire non-traditional thinking for future on-chip ESD protection.

π-Shape ESD Protection Design for Multi-Gbps High-Speed Circuits in CMOS Technology

CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustness and performance in high-speed applications.

Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors

The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.

A power supply clamp with self-cutoff the conducted ESD current path mechanism for latch-up free

A power supply clamp with self-cutoff the conducted ESD (electrostatic discharge) current path mechanism for on-chip ESD protection is developed by TCAD simulation and experiments. The proposed clamp consists of SCR (silicon controlled rectifier) acting as ESD protection device between power and ground rail, and control circuit generating cutoff signal. Different from the traditional SCR which increases holding voltage to prevent latch-up, the proposed structure can automatically set block to cut off the conducted SCR after triggered by ESD stress. Simulation analysis and experimental results show that the reported structure presents self-cutoff capability and latch-up free characteristic even under power-on case.

ESD Protection Designs: Topical Overview and Perspective

Electrostatic discharge (ESD) protection remains a major challenge to integrated circuits (ICs), particularly for complex chips implemented at advanced technology nodes. Over decades, substantial advances have been made to on-chip ESD protection. This paper, instead of reviewing various specific ESD protection structures reported, provides an overview of selected key topics on practical ESD protection designs, focusing on new ESD protection concepts and design methodologies, as well as an outlook to future ESD protection designs.

An On-Chip ESD Sensor for Use in Advanced Packaging

Electrostatic discharge (ESD) failure results in about 35% of integrated circuit (IC) field return and causes several billion-dollar losses to the semiconductor industry per year. Most modern ICs include on-chip ESD protection circuitry which comes at the cost of I/O performance. Static charge accumulation during transport and handling may exceed the limits of this ESD protection and cause damage to the ICs. Modern advanced packaging technologies are not amenable to rework if one or more components are ESD compromised. An on-chip ESD sensor is useful in identifying and preventing the assembly of ESD compromised dielets in any advanced packaging technology. Two approaches for on-chip ESD sensor that can be employed on any die, following the ground rules within that technology are presented. Both approaches are designed, simulated, fabricated, and experimentally characterized using GlobalFoundries 22-nm fully depleted silicon-on-insulator (FDSOI) technology. While determining ESD voltage using sensors, we encounter two events that are naturally random. First, ESD is a random event with some probability distribution function (PDF) with respect to voltage. In addition, oxide breakdown within the ESD sensors is also random with a Weibull distribution. A Bayesian method is developed for the estimation of ESD voltage PDF using sensors. Experimental testing of the sensors using an ESD gun and ESD voltage estimation from the number of sensors that broke down is presented. The estimated ESD voltage closely matches the ESD voltage that the dies were subjected to during experimental verification.

Compact ESD Protection Design for CMOS Low-Noise Amplifier

A low-noise amplifier (LNA) is the input part of a radio frequency (RF) transceiver, which is vulnerable to electrostatic discharge (ESD). When ESD events occur, they may change the original characteristics of the LNA, such as gain decrease and noise figure (NF) increase. Dual diodes (DD) with MOS-based power clamp is a traditional on-chip ESD protection circuit, but it has disadvantages of large parasitic capacitance, large turn-on resistance, large layout area, and large leakage current. Therefore, a new compact ESD protection circuit is proposed, which uses stacked diodes with embedded silicon-controlled rectifier (SDeSCR) and SCR-based power clamp to protect the LNA. The proposed design has advantages of low parasitic capacitance, low clamping voltage, high ESD robustness, and compact layout area. In this work, the ESD protection circuit and the ${K}$ -band LNA are fabricated in CMOS technology, and their RF characteristics and ESD robustness are verified.

On-Chip Gate Electrostatic Discharge Protection Design for 900 V Power Metal Oxide Semiconductor Field Effect Transistor Using Punch-Through Diode Without Degrading Switching Loss.

In order to protect the gate oxide from electrostatic discharge (ESD) in power MOSFET, the on-chip ESD protection circuits are required. Zener diode on poly silicon gate was normally used in power device because Zener diode structure was easy to merge with conditions of vertical structure without adding electrode. However, merged Zener diode can make unnecessary gate capacitance, and then switching characteristics are degraded by added capacitance. In this paper, a stacked punch-through diode (PT diode) with lower capacitance than Zener diode was designed for 900 V power MOSFET. The PT diode was consisted on doped polysilicon gate between the gate pad and the source pad. The electrical characteristics of this device was designed and analyzed by TCAD simulation and experiments. On the basis of this analysis, the stacked PT diode for ESD protection was optimized and compared with conventional Zener diode.

On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process

On-chip electrostatic discharge (ESD) protection device with large dimension can sustain high-ESD current, but the parasitic capacitance of the ESD protection device will increase the difficulty of impedance matching and degrade the bandwidth for broadband radio frequency (RF) applications. The traditional distributed ESD protection circuit can achieve good impedance matching, but it has a worse ESD robustness because of larger resistance caused by the input inductor. In this paper, a new distributed ESD protection structure with the stacked diodes with embedded silicon-controlled rectifier is proposed to attain good ESD robustness without degrading the RF performance. The proposed ESD protection circuit has been successfully verified in a 40-nm, 2.5-V CMOS process to sustain a human-metal model of 5 kV. The proposed ESD protection circuit is suitable to protect the broadband RF circuits in advanced nanoscale CMOS technology.

On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. The traditional methods to reduce parasitic capacitance were using a stacked diode or a stacked diode with embedded silicon-controlled rectifier (SCR). The stacked diode or the stacked diode with embedded SCR would have larger turn-on resistance to cause a higher clamping voltage. It should be further improved to achieve good ESD protection effectiveness for the high-speed I/O applications. In this paper, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The measurement results from the silicon chip have demonstrated that the proposed ESD device can achieve smaller parasitic capacitance, lower turn-on resistance, and higher ESD robustness, compared with the conventional devices. The proposed ESD protection device is very suitable to protect the high-speed I/O circuits in nanoscale CMOS technology.

Diode String With Reduced Clamping Voltage for Efficient On-Chip ESD Protection

The standard steps of P− implantation and silicide block in the complementary metal-oxide semiconductor (CMOS) process are used in this design to implement the proposed diode string. The novel diode string realized by the diodes of P+ with N-well (P+/NW) and P− with N+ (P−/N+) is proposed in this letter. Besides, two diodes are merged together to form a silicon-controlled rectifier path to reduce the clamping voltage during electrostatic discharge (ESD) stress. The test devices of prior and proposed diode strings have been compared in a 0.18 ${\mu }\text{m}$ CMOS process. With the higher current-handling ability and lower clamping voltage, the proposed diode string can be used as the efficient on-chip ESD protection device.

Systematic Characterization of Graphene ESD Interconnects for On-Chip ESD Protection

We report systematic transient characterization of a graphene ribbon (GR) used as an interconnect for electrostatic discharge (ESD) protection of future integrated circuits. A large set of GR wires (around 6000) with varying and practical dimensions were fabricated using the chemical vapor deposition method and characterized by transmission line pulsing (TLP) and very fast TLP (VFTLP) measurements. Comprehensive TLP and VFTLP testing with varying pulse rise time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{r})$ </tex-math></inline-formula> and duration ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{d})$ </tex-math></inline-formula> was performed across a wide temperature range ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T = -30/+110~^{\circ }\text{C}$ </tex-math></inline-formula> ). Measurement-based statistics reveal the relationship between ESD capability of GR wires and the wire length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L$ </tex-math></inline-formula> ), width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> ), and number of graphene layers, as well as ESD pulse shapes and operation temperature.

Area-Efficient and Low-Leakage Diode String for On-Chip ESD Protection

Diode string was used as the effective on-chip electrostatic discharge (ESD) protection device. To reduce the leakage current and the layout area, an area-efficient and low-leakage diode string is proposed in this paper. The standard steps of P− implantation and silicide blocking in CMOS process are used in this design to realize the proposed diode string with stacked P−/N+ diodes. The test devices of the proposed design have successfully been verified in the silicon chip. With the high ESD robustness, low leakage current, and small layout area, the proposed diode string can be a better solution for on-chip ESD protection applications.

Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process

This work presents the design of a novel static-triggered power-rail electrostatic discharge (ESD) clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit (TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current (Ileak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.

Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process

A novel, area-efficient transient power-rail electrostatic discharge (ESD) clamp circuit is proposed in this work. Current-mirror capacitors are used to reduce the layout area. Logic threshold voltages of inverters are modified to ensure a fully active on-state for the clamp device in ESD conditions. The proposed circuit reduces the layout area by about 56% compared with a circuit without current-mirror capacitors. Transmission line pulse (TLP) test results based on a 65-nm CMOS process demonstrate that the proposed circuit is an efficient on-chip ESD protection scheme for this process. In addition, the proposed circuit achieves a good immunity to mis-triggering with respect to fast power-up transitions.

Robust dual-direction SCR with low trigger voltage, tunable holding voltage for high-voltage ESD protection

An LDNMOS-based and an LDPMOS-based dual direction silicon controlled rectifier (DDSCR) devices have been designed and fabricated in a 0.5-μm 5V/18V high voltage (HV) CDMOS process. These devices can be used to protect pins with a voltage range that goes above and below the ground by discharging electrostatic current in both positive and negative directions. A 2-dimension (2D) device simulation and a transmission line pulse (TLP) measurement were used to predict and characterize the ESD performance of the two DDSCR devices. Compared to LDNMOS-based DDSCR, LDPMOS-based DDSCR is excellent for its relatively low trigger voltage of 33V and strong electrostatic discharge (ESD) current handling capability of 87mA/μm. Furthermore, the holding voltage of LDPMOS-based DDSCR can be elevated by tuning layout parameter. Such a device has been applied to I/O bus terminals of a data interface circuit for its on-chip ESD protection.