An On-Chip ESD Sensor for Use in Advanced Packaging

Abstract

Electrostatic discharge (ESD) failure results in about 35% of integrated circuit (IC) field return and causes several billion-dollar losses to the semiconductor industry per year. Most modern ICs include on-chip ESD protection circuitry which comes at the cost of I/O performance. Static charge accumulation during transport and handling may exceed the limits of this ESD protection and cause damage to the ICs. Modern advanced packaging technologies are not amenable to rework if one or more components are ESD compromised. An on-chip ESD sensor is useful in identifying and preventing the assembly of ESD compromised dielets in any advanced packaging technology. Two approaches for on-chip ESD sensor that can be employed on any die, following the ground rules within that technology are presented. Both approaches are designed, simulated, fabricated, and experimentally characterized using GlobalFoundries 22-nm fully depleted silicon-on-insulator (FDSOI) technology. While determining ESD voltage using sensors, we encounter two events that are naturally random. First, ESD is a random event with some probability distribution function (PDF) with respect to voltage. In addition, oxide breakdown within the ESD sensors is also random with a Weibull distribution. A Bayesian method is developed for the estimation of ESD voltage PDF using sensors. Experimental testing of the sensors using an ESD gun and ESD voltage estimation from the number of sensors that broke down is presented. The estimated ESD voltage closely matches the ESD voltage that the dies were subjected to during experimental verification.