Abstract
Electrostatic discharge (ESD) protection remains a major challenge to integrated circuits (ICs), particularly for complex chips implemented at advanced technology nodes. Over decades, substantial advances have been made to on-chip ESD protection. This paper, instead of reviewing various specific ESD protection structures reported, provides an overview of selected key topics on practical ESD protection designs, focusing on new ESD protection concepts and design methodologies, as well as an outlook to future ESD protection designs.
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