On-chip Bus Research Articles

On-Chip Bus Arbiter Testing and Verification in FPGA

On-Chip Bus Arbiter Testing and Verification in FPGA

The Efficient On-Chip Bus Architecture for High-Performance SoC Design

The Efficient On-Chip Bus Architecture for High-Performance SoC Design

On-Chip AMBA Bus Based Efficient Bridge between High Performance and Low Peripheral Devices

Today’s scenario of SOC deals with integrity and sharing of information or data with various level of communication. AMBA bus protocol has been proposed by ARM community to justify the uneven demand of integrity .In this paper functional description and implementation of high peripheral devices supporting protocol AXI2.0 and its interface between low peripheral devices has been proposed. The connection named as bridge take care of the protocol mismatch and operates on data transfer for uneven speed demand. Asynchronous FIFO has been considered to avoid the complex handshaking mechanism. The design has been implemented within VHDL and implemented on Xilinx Virtex 4.

Improving fault-tolerance capability of on-chip binary CDMA bus

Shrinking technology and growing complexity of the contemporary system on chip designs require high performance and reliable interconnection architecture. Binary CDMA on-chip bus permits simultaneous use of the shared communication medium by multiple data streams and alleviates contention and queuing delays experienced by a conventional time-division multiplexing shared bus. In this paper, we present an encoding scheme for improving reliability of the on-chip interconnect system based on a binary CDMA bus. Without adding extra wires to the bus, the proposed encoding method replaces the standard binary encoding with a non-weighted code which tolerates single-bit error at any bus wire within the timing window of a single CDMA transaction. In addition, we derive constraints for a codeword selection under which the single-bit error tolerance is achieved and provide a recursive algorithm for code construction. Simulation results show that the proposed encoding scheme significantly improves the post-decoding bit error rate performance of the binary CDMA bus under a binary symmetric channel model.

A novel bus transfer mode (AS transfer) and a performance evaluation methodology

This paper proposes an innovative on-Chip bus transfer mode – the Advanced Encryption Standard (AES) state transfer (AS) and a performance evaluation methodology to estimate the transfer performance. By modeling and collecting several performance metrics including bus latency, bandwidth, valid bandwidth, power and energy consumption using the methodology, it enhances fidelity of the performance analysis and evaluation. As a case study, we formally complete the hardware implementation flow on Advanced High-Performance Bus (AHB), Advanced eXensible Interface 4 (AXI4) and AS bus (ASBUS) DMA, and demonstrate high estimation accuracy by comparing all the experimental results. Both static analysis and hardware implementation results show that the data transfer latency is close to 29% of AHB and 58% of AXI4 by using the AS transfer. Moreover, it is observed that this high-efficiency transfer mode of ASBUS helps to enhance the valid data bandwidth to around 3.4 times that of AHB and 1.7 times that of AXI4, and the energy consumption of ASBUS is only a half of AHB and AXI4. Furthermore, the proposed evaluation methodology is effectively used with sufficient accuracy (the average estimation error: 3.3%) in the design flow.

A High-Performance On-Chip Bus (MSBUS) Design and Verification

This brief proposes a high-performance system-on-chip bus protocol termed the master-slave bus (MSBUS). Considering the inevitable tradeoff among area, throughput and energy efficiency, the control bus is developed as a low-cost and low-power bus, and the data bus is created as a high-throughput full-duplex bus with the feature of block data transfer. To evaluate the bus performance, we create four analytical models including transfer time consumption (TC), wire efficiency (WE), valid data bandwidth (VDB) and dynamic energy efficiency. Then, the advanced high-performance bus-, advanced eXensible interface (AXI)-, and MSBUS-based direct memory access (DMA) are developed as a case study of hardware implementation. It is observed that MSBUS DMA costs less hardware resources and achieves higher performance, especially in the block transfer mode. For instance, the results from both the analytical models and the practical tests show that the TC of MSBUS is close to 63% of the AXI, the WE and VDB of MSBUS are almost 2.3 and 1.6 times of the AXI respectively, and the energy consumption is half of AXI in the block transfer mode.

An Offline Method for Designing Adaptive Routing Based on Pressure Model

As a scalable substitute of on-chip bus, network-on-chip (NoC) is proposed as the communication infrastructure in modern multi/many-core system-on-chip (SoC). Efficient communication in NoC is critical to the overall SoC performance. Although local congestion has an important impact on communication delay, it is barely taken into account when designing routing algorithms. In this paper, we propose an offline methodology of designing routing algorithm based on channel pressure model to address the local congestion issue. Specifically, the proposed methodology uses divide-conquer with the aim of generating high performance routing algorithms, which are able to balance the load over the network with a consequent reduction of local congestion. By using the proposed methodology, the obtained routing could achieve up to 37% performance improvement (in terms of average communication delay) as compared to the well-known odd-even routing algorithm for $15\times 15$ network.

English

This paper gives a brief description of various on-chip bus protocols such as the Advanced Microcontroller Bus Architecture (AMBA) Advanced High-Performance bus (AHB) and Advanced Extensible Interface (AXI), Wishbone Bus, Open Core Protocol (OCP) and CoreConnect Bus. It gives a brief introduction of high performance system-on-chip bus protocol termed as the master-slave bus (MSBUS). By taking into consideration the inevitable trade-off among area, throughput and energy efficiency, the control bus is developed as low-cost and lowpower bus whereas the data bus is created as a high-throughput full-duplex bus. This on-chip bus protocol is differentiated from other on-chip bus protocols with feature of efficient block data transfer. This MSBUS is an effective bus protocol in many applications such as image processing, computer vision, and wireless communication where it requires less hardware resources and achieves higher performance, especially in block transfer mode. The comparison is made between different protocols with respect to various parameters.

A Theoretical Analysis of Fibonacci Coding Techniques on On-chip Data Bus

As VLSI technology has scaled down towards the Deep Sub-micrometer (DSM) technology the crosstalk delay is flattering a great part of the total delay of a circuit. In addition, the escalating of cross-coupling capacitances among on-chip bus wires on the identical metal layer generates a situation where the delay of a wire is effectively relying on the electrical status of its adjacent wires. Therefore the data patterns on the on-chip data bus will affect the crosstalk delay. In this Paper, the performance of the Fibonacci coding techniques with respect to transition energy and crosstalk delay has been carried out and compared between them. The simulation results show that the NFF, RF and CRF coding technique offers on average ∼50% energy savings and average ∼30% delay reduction. So the entire system performance increases while the crosstalk delay reduces. Hence, these coding techniques increase the speed of the bus and/or diminish the total energy dissipation.

Symbolic Model Checking of WISHBONE on-Chip Bus

Symbolic Model Checking of WISHBONE on-Chip Bus

Error Correction Encoding for Tightly Coupled On-Chip Buses

The performance of a tightly coupled on-chip bus connecting several embedded cores can be improved using multithreshold comparators at the receiver end. Reduction in supply voltage may cause bit errors. An on-chip encoding technique for error correction is proposed to improve the robustness of the method. It relies on a novel algorithmic formulation that exploits the inbuilt redundancy of the multithreshold architecture to reduce the number of redundant bits required to achieve error correction when compared with the existing methods. Extensive experimental evaluation confirms that the overhead of the proposed encoding technique is significantly less than that of the traditional encoding techniques that use a single threshold voltage. Experimental evidence demonstrates that the proposed encoding technique can be implemented on-chip in a scalable nonenumerative manner.

A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets

Multicore technology has the potential for drastically increasing productivity of embedded real-time computing. However, joint use of hardware, e.g., caches, memory banks and on-chip buses makes the integration of multiple real-time applications into a single system difficult: resource accesses are exclusive and need to be sequenced. Moreover, resource access schemes of modern off-the-shelf multicore chips are commonly optimized for the average-case, rather than being timing predictable. Real-time analysis for such architectures is complex, as execution times depend on the deployed hardware, as well as on the software executing on other cores. This will ask for significant abstractions in the timing analysis, where the resulting pessimism will lead to over-provisioned system designs and a lowered productivity as the number of applications to be put together into a single architecture needs to be decreased. In response to this, (a) we present a formal approach for bounding the worst-case response time of concurrently executing real-time tasks under resource contention and almost arbitrarily complex resource arbitration policies, with a focus on main memory as shared resource, (b) we present a simulation framework which allows for detailed modeling and empirical evaluation of modern multicore platforms and applications running on top of them, and (c) we present experiments to demonstrate the advantages and disadvantages of the presented methodologies and compare their accuracy. For limiting non-determinism inherent to the occurrence of cache misses, we particularly take advantage from the predictable execution model as discussed in recent works.

Design of Router Supporting Multiply Routing Algorithm for NoC

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

Improved Analytical Delay Models for RC-Coupled Interconnects

As process technologies scale into deep submicrometer region, crosstalk delay is becoming increasingly severe, especially for global on-chip buses. To cope with this problem, accurate delay models of coupled interconnects are needed. In particular, delay models based on analytical approaches are desirable, because they are not only largely transparent to technology, but also explicitly establish the connections between delays of coupled interconnects and transition patterns, thereby enabling crosstalk alleviating techniques such as crosstalk avoidance codes. Unfortunately, existing analytical delay models, such as the widely cited model in [1], have limited accuracy and do not account for loading capacitance. In this brief, we propose analytical delay models for coupled interconnects that address these disadvantages.

On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor core, resulting in a high volume of diverse data transfer through the L1-L2 cache bus. High-performance CMP and SoC systems have a significant amount of data transfer between the on-chip L2 cache and the L3 cache of off-chip memory through the power expensive off-chip memory bus. This paper addresses the problem of the high-power consumption of the on-chip data buses, exploring a framework for memory data bus power consumption minimization approach. A comprehensive analysis of the existing bus power minimization approaches is provided based on the performance, power, and area overhead consideration. A novel approaches for reducing the power consumption for the on-chip bus is introduced. In particular, a serialization-widening (SW) of data bus with frequent value encoding (FVE), called the SWE approach, is proposed as the best power savings approach for the on-chip cache data bus. The experimental results show that the SWE approach with FVE can achieve approximately 54% power savings over the conventional bus for multicore applications using a 64-bit wide data bus in 45 nm technology.

On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions

Modern on-chip communication protocols such as advanced eXtensible interface and open core protocol support advanced transactions to improve communication efficiency. Out-of-order transactions that allow responses to be returned in an order different from their request order play an important role in this improvement. However, a deadlock situation may occur if these transactions are not properly manipulated. In this paper, we address the deadlock problem in an on-chip bus system supporting out-of-order transactions. We present a graphic model that can well represent the status of a bus system and show that a cycle exists in the graph if and only if the bus system is in an unsafe state that may lead to a bus deadlock. Based on this model, we propose a novel bus design technique that can efficiently resolve the bus deadlock problem. Experimental results show that buses with the proposed technique can be up to 3.3 times faster than those with the currently available techniques.

Optimization of Delay and Energy in On-Chip Buses using Bus Encoding Technique

In very deep sub-micron (VDSM) fault-tolerant busses, crosstalk noise and logic faults caused due to shrinking wiresize and reduced inter-wire spacing are major factors affecting the performance of onchip interconnects, such as high power consumption and increased delay. In this paper we propose a bus optimization technique which reduce the energy and power-delay using Hamming Single Error Correcting Code. In this coding scheme we implement Fibonacci representation of optimal (7,4) Hamming Code which is more efficient than Single Error correction (9,4) Hamming Code. Also the proposed scheme eliminates crosstalk classes among the interconnects wires, there by reducing delay and energy consumption. The proposed techniques achieves an efficiency of 11% in energy consumption and a reduction of delay with respect to the existing techniques.

An AMBA Advanced High performance Bus Tracer with Real time Compression for Support of SoC

AMBA (Advanced Microcontroller based Bus Architecture) consists of AHB (Advanced High performance Bus), APB (Advanced Peripheral Bus), ASB (Advanced System Bus) and AXI (Advanced extensible Bus). This Paper proposes the debugging and analyses of system on chip (SoC) at various test conditions by verifying the functional aspects of the on-chip bus. Here we select an Advanced High performance bus (AHB), since the AHB bus signals are hard to examine as they are extremely embedded in the system on chip and there are no sufficient I/O pins to access these signals. Hence we embed a bus tracer in SoC to capture and compress the bus signals with different compression mechanisms. The tracer is successfully verified in FPGA SPARTAN 3E (XC3S500E). Tools used in this manuscript Modelsim for simulation and XILINX ISE II for RTL Synthesis.

On-Chip Bus Designing with the Interface of Open Core Protocol

As more and more IP cores are integrated into an SOC design, the communication flow between IP cores has increased drastically and the efficiency of the on-chip bus has become a dominant factor for the performance of a system. The on-chip bus design can be divided into two parts, namely the interface and the internal architecture of the bus. In this work we adopt the well-defined interface standard, the Open Core Protocol (OCP), and focus on the design of the internal bus architecture. We develop an efficient bus architecture to support most advanced bus functionalities defined in OCP, including burst transactions, lock transactions, pipelined transactions, and out of-order transactions. We first model and design the on-chip bus with transaction level modeling for the consideration of design flexibility and fast simulation speed. We then implement the RTL models of the bus for synthesis and gate-level simulation. Experimental results show that the proposed TLM model is quite efficient for the whole system simulation and the real implementation can significantly save the communication time.

A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS

The unrelenting demands of wireless/multimedia DSP workloads necessitate specialized hardware to achieve higher performance and power efficiency. Razor systems offer even greater power efficiency by minimizing static supply voltage (VDD) guardbands for process/voltage/temperature (PVT) variation, while also providing a degree of resilience to general delay faults (e.g. SEUs). To date, Razor has only been demonstrated on silicon in the context of microprocessor pipelines [1][2]. Reported Algorithmic Noise Tolerance (ANT) circuits [3][4] operate at very high error rates, but rely on imbalanced ripple-carry adders and hence clock frequency (Fclk) is limited (50-88MHz). ANT also requires additional datapaths for error detection/correction, which cannot be clock gated in the absence of errors, increasing baseline area and power. Combining Razor error detection with algorithm-level correction enables high-Fclk datapaths and low-overheads. A 0.19mm2 16-tap Razor FIR datapath is fabricated in 65nm LP CMOS, with input and output SRAMs, tunable pulse-clock generator, BIST logic and an AHB slave on-chip bus interface (Fig. 24.5.1), demonstrating: 1) two distinct fixed-latency Razor error-correction techniques for real-time DSP datapaths: time-borrow tracking (TBT) and interpolation-based approximate error correction (AEC); 2) a Razor latch (RZL) circuit with reduced pessimism; 3) a 1GHz datapath, an order of magnitude improvement over [3][4] due to elimination of ripple-carry adders; 4) energy efficiency improvement of up to 37%.