Improving fault-tolerance capability of on-chip binary CDMA bus

Abstract

Shrinking technology and growing complexity of the contemporary system on chip designs require high performance and reliable interconnection architecture. Binary CDMA on-chip bus permits simultaneous use of the shared communication medium by multiple data streams and alleviates contention and queuing delays experienced by a conventional time-division multiplexing shared bus. In this paper, we present an encoding scheme for improving reliability of the on-chip interconnect system based on a binary CDMA bus. Without adding extra wires to the bus, the proposed encoding method replaces the standard binary encoding with a non-weighted code which tolerates single-bit error at any bus wire within the timing window of a single CDMA transaction. In addition, we derive constraints for a codeword selection under which the single-bit error tolerance is achieved and provide a recursive algorithm for code construction. Simulation results show that the proposed encoding scheme significantly improves the post-decoding bit error rate performance of the binary CDMA bus under a binary symmetric channel model.