On-chip Architecture Research Articles

Dynamic Clock Switching Scheme for Enhanced Power Efficiency in System-on-Chip Architectures

High power consumption and thermal management are critical challenges in traditional System- on-Chip (SoC) architectures due to multiple active clock sources feeding individual IP blocks, even during idle states. This paper introduces a dynamic clock switching power-saving scheme that consolidates clock sources by dynamically switching to a single lower-frequency clock during low-power modes. A Clock Control Agent (CCA) monitors real-time operational status, power consumption, and performance needs, leveraging AI for predictive adjustments. Experimental results demonstrate a significant reduction in idle power consumption and improved thermal management, without compromising performance or data integrity. This scheme addresses inefficiencies in existing methods such as Dynamic Voltage and Frequency Scaling (DVFS) and clock gating, offering a robust and efficient solution for next-generation SoC designs.

Signal Crosstalk in a Flip-Chip Quantum Processor

Quantum processors require a signal-delivery architecture with high addressability (low crosstalk) to ensure high performance already at the scale of dozens of qubits. Signal crosstalk causes inadvertent driving of quantum gates, which will adversely affect quantum gate fidelities in scaled-up devices. Here, we demonstrate packaged flip-chip superconducting quantum processors with signal-crosstalk performance competitive with those reported in other platforms. For capacitively coupled qubit-drive lines, we find on-resonant crosstalk better than −27 dB (average −37 dB). For inductively coupled magnetic-flux-drive lines, we find less than 0.13% direct-current flux crosstalk (average 0.05%). These observed crosstalk levels are adequately small and indicate a decreasing trend with increasing distance, which is promising for further scaling up to larger numbers of qubits. We discuss the implications of our results for the design of a low-crosstalk on-chip signal-delivery architecture, including the influence of a shielding tunnel structure, potential sources of crosstalk, and estimation of crosstalk-induced qubit-gate error in scaled-up quantum processors. Published by the American Physical Society 2024

Unidirectional and hierarchical on-chip interconnected architecture for large-scale hardware spiking neural networks

Spiking Neural Networks (SNNs) exhibit the strong capability to address spatiotemporal dynamic problems. Recent research has explored the hardware SNN systems to solve the spatiotemporal problems in real-time. The Network-on-Chip (NoC) is an effective scheme for building large-scale hardware SNNs. However, for the existing NoC-based hardware SNNs, large area overhead and hardware power are consumed by their interconnections, because of complex topologies and router structures. Therefore, in this work a novel Unidirectional and Hierarchical on-Chip Interconnected Architecture (UHCIA) is proposed to address this problem. The proposed UHCIA mainly combines the novel hybrid topology of unidirectional multiple loops and rings, and uses a deflection router technique. Experimental results show that compared to other works, the UHCIA achieves ∼23.6X of area reduction and ∼6.4X of power reduction, with high system throughput and biological real-time computations.

Probability-based mapping approach for an application-aware networks-on-chip architectures

In a digital and automation era, on-chip multi-core architecture plays a vital role in effective communication in the field of very large-scale integrated circuits (VLSI). In this paper, we propose a unique mapping approach in which a probability-based core selection from the application benchmark into the center to eccentric way of placement of cores in the standard network architecture improves the performance of networks-on-chip (NoC). The proposed approach utilizes a structured mapping strategy, in contrast to the random mapping. This characteristic renders the proposed method a robust solution for a diverse range of NoC architectures irrespective of scale. The proposed approach provides better quality of service (QoS) with optimal total communication bandwidth and average hop count. The performance of the proposed mapping approach is validated with various experiments over standard and real-time benchmarks. The investigation results indicate that the total communication cost over real-time NoC benchmarks for the proposed mapping approach offers 43.06%, 22.75%, and 16.69% average improvement over CastNet, NMAP, and mapGtoM respectively. Furthermore, we adopt uniform geometric and shuffled traffic patterns to identify the latency and throughput of the proposed probability-based mapping approach. The investigation results indicate that the proposed mapping approach outperforms existing mapping procedures.

A Vacuum Waveguide Filter Bank Spectrometer for Far-Infrared Astrophysics

Traditional technologies for far-infrared (FIR) spectroscopy generally involve bulky dispersive optics. Integrated filter bank spectrometers promise more compact designs, but implementations using superconducting transmission line networks become lossy at terahertz frequencies. We describe a novel on-chip spectrometer architecture designed to extend this range. A filter bank spectrometer is implemented using vacuum waveguide etched into a silicon wafer stack. A single trunk line feeds an array of resonant cavities, each coupled to a kinetic inductance detector fabricated on an adjacent wafer. We discuss the design and fabrication of a prototype implementation, initial test results at ambient temperature, and prospects for future development.

Optimizing code allocation for hybrid on-chip memory in IoT systems

With the increasing application of IoT devices, the memory subsystem, as the performance and energy bottleneck of IoT systems, has received a lot of attention. One of the keys is on-chip memory which can bridge the performance gap between the CPU and main memory. While many off-the-shelf embedded processors utilize the hybrid on-chip memory architecture containing scratchpad memories (SPMs) and caches, most existing literature ignores the collaboration between caches and SPMs. This paper proposes static SPM allocation strategies for the architecture mentioned above in IoT systems, which try to minimize the overall instruction memory subsystem latency and/or energy consumption. We capture the intra- and inter-task cache conflict misses via a fine-grained temporal cache behavior model. Based on this cache conflict information, we propose an integer linear programming (ILP) algorithm to generate an optimal static function level SPM allocation for system performance. Furthermore, to improve the scalability of the proposed allocation scheme for an enormous task set, we offer the interference factor to calculate the interference impact quantitatively. Then, based on the interference factor, we present two approximate knapsack based heuristic algorithms to provide near optimal static allocation schemes at both function- and basic block-level granularities, which favors fast design space exploration. The experiment results demonstrate that the proposed solution achieves a 30.85% improvement in memory performance, and up to 31.39% reduction in energy consumption, compared to the existing SPM allocation scheme at the function level. In addition, the proposed basic block level allocation algorithm shows better performance than our function level allocation algorithm and other basic block level allocation algorithm.

Photonic neuromorphic architecture for tens-of-task lifelong learning.

Scalable, high-capacity, and low-power computing architecture is the primary assurance for increasingly manifold and large-scale machine learning tasks. Traditional electronic artificial agents by conventional power-hungry processors have faced the issues of energy and scaling walls, hindering them from the sustainable performance improvement and iterative multi-task learning. Referring to another modality of light, photonic computing has been progressively applied in high-efficient neuromorphic systems. Here, we innovate a reconfigurable lifelong-learning optical neural network (L2ONN), for highly-integrated tens-of-task machine intelligence with elaborated algorithm-hardware co-design. Benefiting from the inherent sparsity and parallelism in massive photonic connections, L2ONN learns each single task by adaptively activating sparse photonic neuron connections in the coherent light field, while incrementally acquiring expertise on various tasks by gradually enlarging the activation. The multi-task optical features are parallelly processed by multi-spectrum representations allocated with different wavelengths. Extensive evaluations on free-space and on-chip architectures confirm that for the first time, L2ONN avoided the catastrophic forgetting issue of photonic computing, owning versatile skills on challenging tens-of-tasks (vision classification, voice recognition, medical diagnosis, etc.) with a single model. Particularly, L2ONN achieves more than an order of magnitude higher efficiency than the representative electronic artificial neural networks, and 14× larger capacity than existing optical neural networks while maintaining competitive performance on each individual task. The proposed photonic neuromorphic architecture points out a new form of lifelong learning scheme, permitting terminal/edge AI systems with light-speed efficiency and unprecedented scalability.

Model and analysis of the data readout architecture for the ITS3 ALICE Inner Tracker System

The ALICE collaboration is developing the Inner Tracker System 3 (ITS3), a novel detector that exploits the stitching technique to construct single-die monolithic pixel sensors of up-to 266 mm × 93 mm. ITS3 requires all hits from a particle flux of 5.75 MHz/cm2 to be transmitted on-chip to one of the sensor edges. This on-chip readout must balance the resources of power consumption, dead area, and readout performance by tuning different design parameters such as on-chip memories or on-chip links bandwidth. For doing so, a model of the ITS3 on-chip readout architecture will be presented. This model combines an accurate simulation of the particle flux fluctuations expected in ALICE with a clock-accurate digital readout simulator, combining high accuracy with fast code in terms of simulation speed.

Comparative analysis of 2D mesh topologies with additional communication links for on-chip networks

Multiprocessor system-on-chip (MPSoC) is playing a vital role in recent embedded technologies. One of the main challenges of this system is its communication bottleneck which limits performance scaling capabilities. In order to overcome this restriction, on-chip interconnection networks have been proposed. Several topologies have been suggested in the literature, but the most popular one remains the mesh topology due to its systematic and scalable design structure. Although, the functionality and performance of network-based mesh topologies degrade significantly with growing system size, which results in the network diameter and the dependency on small bisection width. A wide range of modified designs has been proposed in the literature with various types of additional links to improve the network performance. However, these links result in additional cost overhead on the system in terms of area, energy, and power consumption. Among the selected competitor meshes, it is observed that the link design of d-Torus produces high performance at elevated communication costs. The design of the CBP-Torus is less complex and results in lower communication costs compared to d-Torus with similar performance. The selection of an appropriate mesh-type topology of the target application is, therefore, a tradeoff between the performance and cost of the network. This paper analyzes the impact of additional links on the performance of on-chip mesh architectures. The comparative analysis includes performance characteristics, structural complexity, power consumption, and area utilization. This research work provides a roadmap for the designers to choose the most appropriate topology for a particular design.

High-areal capacity Si architecture as an on-chip anode for lithium-ion batteries

Silicon is one of the most promising anode materials for Li-ion batteries, especially to meet the growing demand for energy storage in the form of microbatteries for mobile and autonomous devices. However, the development of such batteries is hindered by mechanical and electrochemical failures resulting from massive Si volume expansion and continuous growth of the solid electrolyte interphase. In this study, we propose a novel on-chip anode architecture using rapid thermal annealing on porous silicon. The structure consists of a densified silicon layer on top of an isotropic structure of a porous layer. We demonstrate that this structure enhances both electrochemical and mechanical stabilities, achieving an areal capacity of 9 mAh cm−2 over more than 200 cycles with a high Coulombic efficiency near 100%.

Strain-induced self-rolled-up microtubes for multifunctional on-chip microfluidic applications.

On-chip microfluidics are characterized as miniaturized devices that can be either integrated with other components on-chip or can individually serve as a standalone lab-on-a-chip system for a variety of applications ranging from biochemical sensing to macromolecular manipulation. Heterogenous integration with various materials and form factors is, therefore, key to enhancing the performance of such microfluidic systems. The fabrication of complex three-dimensional (3D) microfluidic components that can be easily integrated with other material systems and existing state-of-the-art microfluidics is of rising importance. Research on producing self-assembled 3D architectures by the emerging self-rolled-up membrane (S-RuM) technology may hold the key to such integration. S-RuM technology relies on a strain-induced deformation mechanism to spontaneously transform stacked thin-film materials into 3D cylindrical hollow structures virtually on any kind of substrate. Besides serving as a compact microfluidic chamber, the S-RuM-based on-chip microtubular architecture exhibits several other advantages for microfluidic applications including customizable geometry, biocompatibility, chemical stability, ease of integration, uniform field distributions, and increased surface area to volume ratio. In this Review, we will highlight some of the applications related to molecule/particle sensing, particle delivery, and manipulation that utilized S-RuM technology to their advantage.

AdaTest: Reinforcement Learning and Adaptive Sampling for On-chip Hardware Trojan Detection

This paper proposes AdaTest, a novel adaptive test pattern generation framework for efficient and reliable Hardware Trojan (HT) detection. HT is a backdoor attack that tampers with the design of victim integrated circuits (ICs) . AdaTest improves the existing HT detection techniques in terms of scalability and accuracy of detecting smaller Trojans in the presence of noise and variations. To achieve high trigger coverage, AdaTest leverages Reinforcement Learning (RL) to produce a diverse set of test inputs. Particularly, we progressively generate test vectors with high ‘reward’ values in an iterative manner. In each iteration, the test set is evaluated and adaptively expanded as needed. Furthermore, AdaTest integrates adaptive sampling to prioritize test samples that provide more information for HT detection, thus reducing the number of samples while improving the samples’ quality for faster exploration. We develop AdaTest with a Software/Hardware co-design principle and provide an optimized on-chip architecture solution. AdaTest’s architecture minimizes the hardware overhead in two ways: (i) Deploying circuit emulation on programmable hardware to accelerate reward evaluation of the test input; (ii) Pipelining each computation stage in AdaTest by automatically constructing auxiliary circuit for test input generation, reward evaluation, and adaptive sampling. We evaluate AdaTest’s performance on various HT benchmarks and compare it with two prior works that use logic testing for HT detection. Experimental results show that AdaTest engenders up to two orders of test generation speedup and two orders of test set size reduction compared to the prior works while achieving the same level or higher Trojan detection rate.

On-Chip Optical Switching Network Architecture Based on Hybrid Wavelength and Mode Division Multiplexing

On-Chip Optical Switching Network Architecture Based on Hybrid Wavelength and Mode Division Multiplexing

Microbatteries with twin-Swiss-rolls redefine performance limits in the sub-square millimeter range.

To maintain the downscaling of microelectronic devices with footprints less than one square millimeter, next-generation microbatteries should occupy the same area and deliver adequate energy for running a new generation of multi-functional microautonomous systems. However, the current microbattery technology fails in accomplishing this task because the micrometer-sized electrodes are not compatible with on-chip integration protocols and technologies. To tackle this critical challenge, an on-chip Swiss-roll microelectrode architecture is employed that exploits the self-assembly of thin films into ultra-compact device architectures. A twin-Swiss-roll microelectrode on a chip occupies a footprint of 0.045 mm2 and delivers an energy density up to 458 μW h cm-2. After packaging, the footprint of a full cell increases to 0.11 mm2 with a high energy density of 181 μW h cm-2. The volumetric energy density excluding the chip thickness is 16.3 mW h cm-3. These results open opportunities for deploying microbatteries as energy and power sources to drive smart dust microelectronics and microautonomous systems.

Development of Superconducting On-chip Fourier Transform Spectrometers.

Superconducting On-chip Fourier Transform Spectrometers (SOFTS) are broadband, ultra-compact and electronic interferometers. SOFTS will enable kilo-pixel spectro-imaging focal planes, enhancing sub-millimeter astrophysics and cosmology. Particular applications include cluster astrophysics, cosmic microwave background (CMB) science, and line intensity mapping. This article details the development, design and bench-marking of radio frequency (RF) on-chip architecture of SOFTS for Ka and W-bands.

An Ultra-Energy-Efficient and High Accuracy ECG Classification Processor With SNN Inference Assisted by On-Chip ANN Learning.

The ECG classification processor is a key component in wearable intelligent ECG monitoring devices which monitor the ECG signals in real time and detect the abnormality automatically. The state-of-the-art ECG classification processors for wearable intelligent ECG monitoring devices are faced with two challenges, including ultra-low energy consumption demand and high classification accuracy demand against patient-to-patient variability. To address the above two challenges, in this work, an ultra-energy-efficient ECG classification processor with high classification accuracy is proposed. Several design techniques have been proposed, including a reconfigurable SNN/ANN inference architecture for reducing energy consumption while maintaining classification accuracy, a reconfigurable on-chip learning architecture for improving the classification accuracy against patent-to-patient variability, and a dual-purpose binary encoding scheme of ECG heartbeats for further reducing the energy consumption. Fabricated with a 28nm CMOS technology, the proposed design consumes extremely low classification energy (0.3μJ) while achieving high classification accuracy (97.36%) against patient-to-patient variability, outperforming several state-of-the-art designs.

Withdrawal: P. A. Harsha Vardhini and M. Makkena (2022), Design and Comparative Analysis of On‐Chip Sigma Delta ADC for Signal Processing Applications. Advanced Control for Applications: Engineering and Industrial Systems. Accepted Author Manuscript e82. https://doi.org/10.1002/adc2.82

Advent in VLSI technology made digital signal processing to take over analog signal processing. Analog to digital converter plays a vital role in modern digital processing applications. Sigma delta analog to digital converter architecture being digital dominant architecture is much suitable for signal processing applications. This paper presents the design of a low pass continuous time sigma delta analog to digital converter on-chip architecture suitable for signal processing applications with a very few passive components connected externally to FPGA. Schematic level architecture of high-speed comparator working at a differential swing which is not allowed by standard differential pads is designed. By applying various differential swings at the input to LVPECL, the performance and power is analyzed. High performance comparator schematic is designed for On-chip Continuous-time Sigma-delta ADC architecture. Simulations are carried out to verify the maximum input frequency for given RC values. Xilinx provided Spartan 6 I/O pad and package SPICE models are used. Power analysis is carried out with LVPECL logic family based differential buffers along with external RC circuit. The analog and digital sections simulations along with mixed signal simulations at different stages are performed. Power and performance analysis are carried out using H-Spice and Questasim simulations.

Enabling scalable optical computing in synthetic frequency dimension using integrated cavity acousto-optics

Optical computing with integrated photonics brings a pivotal paradigm shift to data-intensive computing technologies. However, the scaling of on-chip photonic architectures using spatially distributed schemes faces the challenge imposed by the fundamental limit of integration density. Synthetic dimensions of light offer the opportunity to extend the length of operand vectors within a single photonic component. Here, we show that large-scale, complex-valued matrix-vector multiplications on synthetic frequency lattices can be performed using an ultra-efficient, silicon-based nanophotonic cavity acousto-optic modulator. By harnessing the resonantly enhanced strong electro-optomechanical coupling, we achieve, in a single such modulator, the full-range phase-coherent frequency conversions across the entire synthetic lattice, which constitute a fully connected linear computing layer. Our demonstrations open up the route toward the experimental realizations of frequency-domain integrated optical computing systems simultaneously featuring very large-scale data processing and small device footprints.

MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs

On-chip memory (usually based on Static RAMs-SRAMs) are crucial components for various computing devices including heterogeneous devices, e.g, GPUs, FPGAs, ASICs to achieve high performance. Modern workloads such as Deep Neural Networks (DNNs) running on these heterogeneous fabrics are highly dependent on the on-chip memory architecture for efficient acceleration. Hence, improving the energy-efficiency of such memories directly leads to an efficient system. One of the common methods to save energy is undervolting i.e., supply voltage underscaling below the nominal level. Such systems can be safely undervolted without incurring faults down to a certain voltage limit. This safe range is also called voltage guardband. However, reducing voltage below the guardband level without decreasing frequency causes timing-based faults. In this paper, we propose MoRS, a framework that generates the first approximate undervolting fault model using real faults extracted from experimental undervolting studies on SRAMs to build the model. We inject the faults generated by MoRS into the on-chip memory of the DNN accelerator to evaluate the resilience of the system under the test. MoRS has the advantage of simplicity without any need for high-time overhead experiments while being accurate enough in comparison to a fully randomly-generated fault injection approach. We evaluate our experiment in popular DNN workloads by mapping weights to SRAMs and measure the accuracy difference between the output of the MoRS and the real data. Our results show that the maximum difference between real fault data and the output fault model of MoRS is 6.21%, whereas the maximum difference between real data and random fault injection model is 23.2%. In terms of average proximity to the real data, the output of MoRS outperforms the random fault injection approach by 3.21x.

Device level reversible potassium intercalation into bilayer graphene

Electrochemical intercalation and storage of alkali metal ions into the graphite interlayer space is a key ingredient for commercial rechargeable ion batteries. While this has been exceptionally fruitful for lithium, the use of other more abundant chemical species such as potassium has fallen behind due to their less favorable ionic radius and host–guest interactions. Here, we deploy a device level on-chip cell architecture to study the reversible intercalation of potassium into the single van der Waals gallery of a graphene bilayer at room temperature and monitor in a time-dependent manner the electronic properties of the graphene bilayer during the insertion and extraction processes. The potassium diffusion is highly reversible and a charge transfer up to about 2.5 × 1013 cm−2 is achieved. The diffusion coefficient well exceeds 10−7 cm2 s−1 at room temperature, an order of magnitude larger than previously reported values in graphite and other compounds.