On-chip Architecture Research Articles

On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems

With the increasing need of computational power the trend towards multicore processors is ubiquitous. The current on-chip architecture comprises multiple cores which usually share last level cache which can be physically distributed on chip. In order to provide system predictability, especially for a real time system where quality of service (QoS) depends on minimum miss rates and low worst case execution time (WCET) for applications running on different cores, efficient cache management techniques are required. Since memory hierarchy and its management is the key of overall system performance and access to off-chip memory for data consumes many clock cycles along with many units of power, it is important to restrict the off-chip access and provide the optimum solution for the on-chip access. To increase performance and energy efficiency various techniques are proposed. This article aims to provide the researchers with the state-of-the-art critical review of the various approaches that focus on data replication and cache partitioning techniques for L3 cache. The existing literature is presented through several classifications based on appropriate design and algorithm. Maintaining energy efficient system is a crucial challenge for multicore processors. This article discusses various techniques which address upscaling performance without compromising on energy efficiency. The article also evaluates cache and/or various processors for high performance applications such as bioinformatics, image & video processing, applications and DSP and IOT. DOI: http://dx.doi.org/10.5755/j01.itc.47.3.18433

Performance-reliability trade-offs in short range RF power amplifier design

In this work, trade-offs between performance and reliability in CMOS RF power amplifiers at the design stage are studied. The impact of transistor sizing, amplifier class and on-chip matching network design are explored for a 130 nm technology and the implications of design decisions in transistor gate oxide reliability are discussed and projected. A strong trade-off is observed between efficiency and reliability, mainly for different on-chip output matching architectures. A comparison between two example designs is performed via SPICE simulations that include reliability models and the effects of aging on the stress conditions of each amplifier.

High Performance Static Segment On-Chip Memory for Image Processing Applications

The performance of the processor core depends on the configuration parameters and utilization of on-chip memory in multimedia applications such as image, video and audio processing. The design of the on-chip memory architecture is critical for power and area efficient design without compromising quality in data-intensive computing applications. This paper proposes a design of high speed, area, and energy efficient Static Segment On-Chip (SSOC) memory for error-tolerant applications. In this static segment method, n-bit data array is reduced by m-bit data array for significant value of input data to achieve balanced design metrics at the cost of accuracy. The proposed m-bit static segmentation algorithm is implemented and verified in Single Port Static Random Access Memory (SP SRAM) architecture for the approximate computing applications. From the overall simulation results, the proposed 4-bit SSOC SP SRAM design provides 49.02% area savings, 50.62% power reduction and 16.92% speed improvement at the cost of 0.64% Peak Signal to Noise Ratio (PSNR) and exhibits same visual quality in comparison with the existing 8-bit conventional on-chip SP SRAM design in the image processing applications.

Parallel Multilevel Cell STT-MRAMs for Optimized Area Energy and Read–Write Operations

Spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for the next generation embedded memory applications. The advent of a perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) device has made the STT-MRAM viable for low-power high-density on-chip memory architectures. However, intense research efforts are still required to optimize the single-level cell and multilevel cell (MLC) STT-MRAMs in terms of area, energy, and read–write operations at ultralow power supply voltages. In this paper, a parallel MLC (pMLC) STT-MRAM (20–50 nm) is proposed to provide smaller footprint area, energy efficient, and optimized read–write operations with very low failure probabilities at the supply voltage of 1 V. These designs utilize high- ${k}$ gate dielectric gate-all-around silicon nanowire-based vertical NMOS transistor as a switching device. The PMTJ device is modeled using Verilog-A. The HSPICE simulation results affirm the suitability of pMLC designs, e.g., 3-bit pMLC design exhibits, switching error probability much less than 10−9, and average write energy of <2 pJ with minimum cell-area at the pulsewidth of 10 ns.

Smart Phase Tuning in Microwave Photonic Integrated Circuits Toward Automated Frequency Multiplication by Design

ABSTRACTThe author investigates the monitoring methods for fine adjustment of the previously proposed on-chip architecture for frequency multiplication and translation of harmonics by design. Digital signal processing (DSP) algorithms are utilized to create an optimized microwave photonic integrated circuit functionality toward automated frequency multiplication. The implemented DSP algorithms are formed on discrete Fourier transform and optimization-based algorithms (Greedy and gradient-based algorithms), which are analytically derived and numerically compared based on the accuracy and speed of convergence criteria.

High-level synthesis of on-chip multiprocessor architectures based on answer set programming

We present a system-level synthesis approach for heterogeneous multi-processor on chip, based on Answer Set Programming(ASP). Starting with a high-level description of an application, its timing constraints and the physical constraints of the target device, our goal is to produce the optimal computing infrastructure made of heterogeneous processors, peripherals, memories and communication components. Optimization aims at maximizing speed, while minimizing chip area. Also, a scheduler must be produced that fulfills the real-time requirements of the application. Even though our approach will work for application specific integrated circuits, we have chosen FPGA as target device in this work because of their reconfiguration capabilities which makes it possible to explore several design alternatives. This paper addresses the bottleneck of problem representation size by providing a direct and compact ASP encoding for automatic synthesis that is semantically equivalent to previously established ILP and ASP models. We describe a use-case in which designers specify their applications in C/C++ from which optimum systems can be derived. We demonstrate the superiority of our approach toward existing heuristics and exact methods with synthesis results on a set of realistic case studies.

SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing

Networks-on-chips (NoCs) are gaining in popularity as replacement for shared medium interconnects in chip-multiprocessors (CMPs) and multiprocessor systems-on-chips, and their performance becoming essential to system performance. There have been emerging studies to achieve better power/energy efficiency without performance degradation on NoCs. However, there are still non-negligible latency issues caused by the mechanism of power efficient approaches. To alleviate the latency problem and to transfer data efficiently with the high utilization of interconnect resources, we propose an on-chip network architecture that improves latency and bandwidth. Increasing the data/link widths across the network may considerably resolve this problem but is a costly proposition both in terms of device area and of power. Alternatively, we propose a dual-path router architecture that efficiently exploits path diversity to attain low latency without significant hardware overhead. By: 1) doubling the number of injection and ejection ports; 2) splitting packets into two halves; 3) recomposing routing policy to support path diversity; and 4) provisioning the network hardware design, we can considerably enhance network resource utilization to achieve much higher performance in latency. The proposed simultaneous dual-path routing (SDPR) scheme outperformed the conventional dimension order routing (DOR) technique across synthetic workloads by 31%–40% in average latency and up to a 100% improvement in throughput performance running on a 49-core CMP. Our synthesizable model for the SDPR router and network provides accurate power and area reports. According to the synthesis reports, SDPR incurs insignificant overhead compared to the baseline XY DOR router.

Power-aware high level evaluation model of interconnect length of on-chip memory network topology

Interconnect power is the factor that dominates the power consumption on the on-chip memory architecture. Almost all dedicated wires and buses are replaced with packet switching interconnection networks which have become the standard approach to on-chip interconnection. Unfortunately, rapid advances in technology are making it more difficult to assess the interconnect power consumption of NoC. To resolve this problem, a new evaluating methodology for interconnect power evaluation based on topology of on-chip memory (IP-ETOM) is proposed in this paper. To validate this method, two multicore architectures 2D-mesh and triplet-based architecture (TriBA) are evaluated in this research work. The on-chip memory network model is evaluated based on characteristics of on-chip architecture interconnection. MATLAB is used for conducting the experiment that evaluates the interconnection power of TriBA and 2D-mesh.

Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network

For Internet of Things (IoT) edge devices, it is very attractive to have the local sensemaking capability instead of sending all the data back to the cloud for information processing. For image pattern recognition, neuro-inspired machine learning algorithms have demonstrated enormous powerfulness. To effectively implement learning algorithms on-chip for IoT edge devices, on-chip synaptic memory architectures have been proposed to implement the key operations such as weighted-sum or matrix-vector multiplication. In this paper, we proposed a low-power design of static random access memory (SRAM) synaptic array for implementing a low-precision ternary neural network. We experimentally demonstrated that the supply voltage (VDD) of the SRAM array could be aggressively reduced to a level, where the SRAM cell is susceptible to bit failures. The testing results from 65-nm SRAM chips indicate that VDD could be reduced from the nominal 1–0.55 V (or 0.5 V) with a bit error rate ~0.23% (or ~1.56%), which only introduced ~0.08% (or ~1.68%) degradation in the classification accuracy. As a result, the power consumption could be reduced by more than $8\times $ (or $10\times $ ).

Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes

Nonvolatile static random access memory (nvSRAM) has been widely investigated as a promising on-chip memory architecture in energy harvesting sensor nodes, due to zero standby power, resilience to power failures, and fast read/write operations. However, conventional approaches back up all data from static random access memory into nonvolatile memory when power failures happen. It leads to significant energy overhead and peak inrush current, which has a negative impact on the system performance and circuit reliability. This paper proposes a holistic data backup optimization to mitigate these problems in nvSRAM, consisting of a partial backup algorithm and a run-time adaptive write policy. A statistic dead-block predictor is employed to achieve dead block identification with trivial hardware overhead. An adaptive policy is used to switch between write-back and write-through strategy to reduce the rollback induced by backup failures. Experimental results show that the proposed scheme improves the performance by 4.6% on average while the backup power consumption and the inrush current are reduced by 38.1% and 54% on average compared to the full backup scheme. What is more, the backup capacitor size for energy buffer can be reduced by 40% on average under the same performance constraint.

Energy-Aware Data Allocation With Hybrid Memory for Mobile Cloud Systems

Resource scheduling is one of the most important issues in mobile cloud computing due to the constraints in memory, CPU, and bandwidth. High energy consumption and low performance of memory accesses have become overwhelming obstacles for chip multiprocessor (CMP) systems used in cloud systems. In order to address the daunting “memory wall” problem, hybrid on-chip memory architecture has been widely investigated recently. Due to its advantages in size, real-time predictability, power, and software controllability, scratchpad memory (SPM) is a promising technique to replace the hardware cache and bridge the processor–memory gap for CMP systems. In this paper, we present a novel hybrid on-chip SPM that consists of a static random access memory (RAM), a magnetic RAM (MRAM), and a zero-capacitor RAM for CMP systems by fully taking advantages of the benefits of each type of memory. To reduce memory access latency, energy consumption, and the number of write operations to MRAM, we also propose a novel multidimensional dynamic programming data allocation (MDPDA) algorithm to strategically allocate data blocks to each memory. Experimental results show that the proposed MDPDA algorithm can efficiently reduce the memory access cost and extend the lifetime of MRAM.

On-Chip Architecture for Self-Homodyned Nonclassical Light

In the last decade, there has been remarkable progress on the practical integration of on-chip quantum photonic devices yet quantum state generators remain an outstanding challenge. Simultaneously, the quantum-dot photonic-crystal-resonator platform has demonstrated a versatility for creating nonclassical light with tunable quantum statistics, thanks to a newly discovered self-homodyning interferometric effect that preferentially selects the quantum light over the classical light when using an optimally tuned Fano resonance. In this work, we propose a general structure for the cavity quantum electrodynamical generation of quantum states from a waveguide-integrated version of the quantum-dot photonic-crystal-resonator platform, which is specifically tailored for preferential quantum state transmission. We support our results with rigorous Finite-Difference Time-Domain and quantum optical simulations, and show how our proposed device can serve as a robust generator of highly pure single- and even multi-photon states.

HTM Spatial Pooler With Memristor Crossbar Circuits for Sparse Biometric Recognition.

Hierarchical Temporal Memory (HTM) is an online machine learning algorithm that emulates the neo-cortex. The development of a scalable on-chip HTM architecture is an open research area. The two core substructures of HTM are spatial pooler and temporal memory. In this work, we propose a new Spatial Pooler circuit design with parallel memristive crossbar arrays for the 2D columns. The proposed design was validated on two different benchmark datasets, face recognition, and speech recognition. The circuits are simulated and analyzed using a practical memristor device model and 0.18 μm IBM CMOS technology model. The databases AR, YALE, ORL, and UFI, are used to test the performance of the design in face recognition. TIMIT dataset is used for the speech recognition.

Exploring the bounds of narrow-band quantum dot downconverted LEDs

Quantum dots are finding increasing commercial success in LED applications. While they have been used for several years in remote off-chip architectures for display applications, it is shown for the first time to our knowledge that quantum dots can withstand the demands of the on-chip architecture and therefore are capable of being used as a direct phosphor replacement in both lighting and display applications. It is well known that, to achieve improved color metrics in lighting as well as increased gamut in display technologies, it is highly desirable to utilize a downconverter with a narrow emission linewidth as well as a precisely tunable peak. This paper will discuss the results of on-chip use of quantum dots in a lighting product, and explore the opportunities and practical limits for improvement of various lighting and display metrics by use of this unique downconverter technology.

Enhanced indistinguishability of in-plane single photons by resonance fluorescence on an integrated quantum dot

Integrated quantum light sources in photonic circuits are envisaged as the building blocks of future on-chip architectures for quantum logic operations. While semiconductor quantum dots have been proven to be the highly efficient emitters of quantum light, their interaction with the host material induces spectral decoherence, which decreases the indistinguishability of the emitted photons and limits their functionality. Here, we show that the indistinguishability of in-plane photons can be greatly enhanced by performing resonance fluorescence on a quantum dot coupled to a photonic crystal waveguide. We find that the resonant optical excitation of an exciton state induces an increase in the emitted single-photon coherence by a factor of 15. Two-photon interference experiments reveal a visibility of 0.80 ± 0.03, which is in good agreement with our theoretical model. Combined with the high in-plane light-injection efficiency of photonic crystal waveguides, our results pave the way for the use of this system for the on-chip generation and transmission of highly indistinguishable photons.

High-Performance and Energy-Efficient Network-on-Chip Architectures for Graph Analytics

With its applicability spanning numerous data-driven fields, the implementation of graph analytics on multicore platforms is gaining momentum. One of the most important components of a multicore chip is its communication backbone. Due to inherent irregularities in data movements manifested by graph-based applications, it is essential to design efficient on-chip interconnection architectures for multicore chips performing graph analytics. In this article, we present a detailed analysis of the traffic patterns generated by graph-based applications when mapped to multicore chips. Based on this analysis, we explore the design-space for the Network-on-Chip (NoC) architecture to enable an efficient implementation of graph analytics. We principally consider three types of NoC architectures, viz., traditional mesh, small-world, and high-radix networks. We demonstrate that the small-world-network-enabled wireless NoC (WiNoC) is the most suitable platform for executing the considered graph applications. The WiNoC achieves an average of 38% and 18% full-system Energy Delay Product savings compared to wireline-mesh and high-radix NoCs, respectively.

Self-homodyne-enabled generation of indistinguishable photons

The rapid generation of non-classical light serves as the foundation for exploring quantum optics and developing applications such as secure communication or generation of NOON-states. While strongly coupled quantum dot-photonic crystal resonator systems have great potential as non-classical light sources due to their promise of tailored output statistics, the generation of indistinguishable photons has been obscured due to the strongly dissipative nature of such systems. Here, we demonstrate that the recently discovered self-homodyne suppression technique can be used to overcome this limitation and tune the quantum statistics of transmitted light, achieving indistinguishable photon emission competitive with state-of-the-art metrics. Furthermore, our nanocavity-based platform directly lends itself to scalable on-chip architectures for quantum information.

Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures

Abstract As embedded systems have evolved to appear in many different domains, symmetric multiprocessing (SMP) has been the design choice from low-end to high-end devices. In this paper we present Prenaut, a design space exploration method for finding the best on-chip SMP architectures given processor cores, Level 1, Level 2, and Level 3 caches. Unlike traditional design space exploration tools that are majorly concerned with optimizations in processor, memory and cache structures with a fixed on-chip architecture, Prenaut explores architectures that have not been considered in symmetric multiprocessing domain. These architectures consist of shared instruction caches between cores and heterogeneous cache topologies that feature bypassing a level in the cache hierarchy. The design idea behind Prenaut is to build a data oriented design space exploration method that exploits simulation data to its full extent rather than discarding it. Therefore, Prenaut uses simulation data and applies machine learning methods for estimating design parameters. This provides very rapid estimation of the Pareto set and guides designers through the overall system design process. The design space is pruned by topological clustering of design points which groups similar topologies and new simulation points are selected via an ordered look up table that prevents infeasible random jumps in the design space. For the selected benchmarks, Prenaut can estimate the Pareto set up to 147x faster and the clustering information can reduce the design space up to 82% in comparison with a state-of-the-art evolutionary algorithm.

Efficient Embedded Software Migration towards Clusterized Distributed-Memory Architectures

A large portion of existing multithreaded embedded sofware has been programmed according to symmetric shared memory platforms where a monolithic memory block is shared by all cores. Such platforms accommodate popular parallel programming models such as POSIX threads and OpenMP. However with the growing number of cores in modern manycore embedded architectures, they present a bottleneck related to their centralized memory accesses. This paper proposes a solution tailored for an efficient execution of applications defined with shared-memory programming models onto on-chip distributed-memory multicore architectures. It shows how performance, area and energy consumption are significantly improved thanks to the scalability of these architectures. This is illustrated in an open-source realistic design framework, including tools from ASIC to microkernel.

Constructive Synthesis of Memory-Intensive Accelerators for FPGA From Nested Loop Kernels

Field-programmable gate arrays are ideal hosts to custom accelerators for signal, image, and data processing but demand manual register transfer level design if high performance and low cost are desired. High-level synthesis reduces this design burden but requires manual design of complex on-chip and off-chip memory architectures, a major limitation in applications such as video processing. This paper presents an approach to resolve this shortcoming. A constructive process is described that can derive such accelerators, including on- and off-chip memory storage from a C description such that a user-defined throughput constraint is met. By employing a novel statement-oriented approach, dataflow intermediate models are derived and used to support simple approaches for on-/off-chip buffer partitioning, derivation of custom on-chip memory hierarchies and architecture transformation to ensure user-defined throughput constraints are met with minimum cost. When applied to accelerators for full search motion estimation, matrix multiplication, Sobel edge detection, and fast Fourier transform, it is shown how real-time performance up to an order of magnitude in advance of existing commercial HLS tools is enabled whilst including all requisite memory infrastructure. Further, optimizations are presented that reduce the on-chip buffer capacity and physical resource cost by up to 96% and 75%, respectively, whilst maintaining real-time performance.