Off-state Breakdown Research Articles

Recess-Free E-Mode AlGaN/GaN MIS-HFET with Crystalline PEALD AlN Passivation Process

We utilized a plasma-enhanced atomic layer deposition (PEALD) process to deposit an AlN passivation layer on AlGaN/GaN surface to enhance the polarization effects, which enabled the fabrication of an enhancement-mode (E-mode) AlGaN/GaN metal-insulator-semiconductor heterojunction field-effect transistor (MIS-HFET) without the need for a gate recess process. The AlN film deposited by PEALD exhibited a crystalline structure, not an amorphous one. The enhanced polarization effect of introducing the PEALD AlN film on a thin AlGaN barrier was confirmed through electrical analysis. To fabricate the E-mode AlGaN/GaN MIS-HFET, the PEALD AlN film was deposited on a 4.5 nm AlGaN barrier layer and then a damage-free wet etching process was used to open the gate region. The MIS-gate structure was formed by depositing a 15 nm plasma-enhanced chemical vapor deposition (PECVD) silicon dioxide (SiO2) film. The fabricated thin-AlGaN/GaN MIS-HFET demonstrated successful E-mode operation, with a threshold voltage of 0.45 V, an on/off ratio of approximately 109, a specific on-resistance of 7.1 mΩ·cm2, and an off-state breakdown voltage exceeding 1100 V.

Epitaxial κ-Ga2O3/GaN heterostructure for high electron-mobility transistors

GaN power technology, especially AlGaN/GaN high electron-mobility transistors (HEMTs), has made significant progress in recent years. However, the performance of HEMTs is still limited due to a trade-off between on-resistance and off-state breakdown voltage (BV). Integrating a polar gate dielectric with GaN HEMTs can potentially improve both sheet resistance of the two-dimensional electron gas channel and the field distribution between gate and drain. In this regard, orthorhombic κ-Ga2O3 has attractive properties since it is predicted to be strongly polar and highly dielectric while it grows epitaxially on GaN. By successfully integrating crystalline κ-Ga2O3 on GaN HEMTs, the channel sheet resistance is reduced by 20% from a reference device with amorphous Al2O3 gate dielectric. As a result, the cut-off frequency increases from 4.8 to 9.1 GHz. The dielectric property of κ-Ga2O3 also improves BV from 354 to 380 V by reducing the peak electric field in the gate-drain region.

Novel Stacked Passivation Structure for AlGaN/GaN HEMTs on Silicon With High Johnson’s Figures of Merit

We present a high-performance AlGaN/GaN high electron mobility transistors (HEMTs) on silicon substrate with novel stacked passivation layer (HfO2/SiO2). The stacked passivation structure can effectively modulate the electric field and reduce the electric field peak on the gate side, thus improving the breakdown voltage of the device. The prepared device with a gate length of 450 nm has a unit current gain cutoff frequency (fT) of 31.5 GHz, a maximum oscillation frequency (fMAX) of 46.3 GHz, and a three-terminal OFF-state breakdown voltage (BVgd) of 140 V at the gate-drain distance of 2.3 μm. The estimated Johnsonfs figure of merit (J-FOM=BVgd×fT) is 4.4 THz∙V, which is three and five times higher than that of the device with single HfO2 passivation layer and single SiO2 passivation layer, respectively. Furthermore, a significant suppression of the current collapse ( 5.7%) is observed due to the electric field redistribution near the drain region. The results show that the AlGaN/GaN HEMTs with stacked passivation layer proved to be a promising candidate for high-performance radio frequency (RF) power device applications.

Performance enhancement for AlGaN/GaN HEMTs with dual discrete field-plate

We propose optimized field plate structures to improve the performance of AlGaN / GaN HEMT under electrical stress. The two structures are T-gate AlGaN / GaN HEMT with dual discrete field plates (DDFP-HEMT) and single discrete field-plate (SDFP-HEMT). Benefiting from the modulation effects of the field plate on the electric field, the DDFP-HEMT and SDFP-HEMT exhibit better breakdown characteristics and current collapse suppression. The performance of the two structure devices and no-discrete-field-plate devices (NDFP- HEMT) is explored in Silvaco TCAD. The DDFP-HEMT and SDFP-HEMT achieve the highest off-state breakdown voltage (VBD) of 1188 V and 1120 V in the experiment, respectively, being 33 % and 25 % higher than that of NDFP-HEMT, respectively. In particular, the current collapse in DDFP-HEMT and SDFP- HEMT is reduced by 24 % and 9 % under 200 V stress bias, respectively, when compared to NDFP-HEMT. The DDFP-HEMT shows greatest reliability improvement in the three samples.

Design and research of normally-off β-Ga2O3/4H-SiC heterojunction field effect transistor

Ga2O3 is difficult to achieve p-type doping, which further hinders the development of Ga2O3-based power devices and is not conducive to the development of new devices with high power density and low power consumption. This paper expounds a β-Ga2O3/4H-SiC heterojunction lateral metal–oxide–semiconductor field-effect transistor (HJFET), which can make better use of the characteristics of PN junction by adding p-doped SiC in the channel region. Compared with the conventional devices, the threshold voltage of the heterojunction metal–oxide–semiconductor field-effect transistor (MOSFET) is greatly improved, and normally-off operation is realized, showing a positive threshold voltage of 0.82 V. Meanwhile, the off-state breakdown voltage of the device is up to 1817 V, and the maximum transconductance is 15.3 mS/mm. The optimal PFOM is obtained by simulating the thickness, length and doping of the SiC in each region of the epitaxial layer. This structure provides a feasible idea for high performance β-Ga2O3 MOSFET.

Surrogate models for device design using sample-efficient Deep Learning

Generation of training dataset for machine learning-based device design algorithm is expensive. To address this, we propose an active learning approach. Its efficiency is demonstrated through a Deep Neural Network (DNN) based Laterally Diffused Metal Oxide Semiconductor Field-effect Transistor (LDMOSFET) off-state breakdown voltage (BVDS,off) and specific on-resistance (Rsp) predictor. Our results show the possibility of ∼50% reduction in the training dataset size without compromising the baseline accuracy. Specifically, we compared eight sampling techniques and found that Informative-Query by Committee (I-QBC) and Diverse Informative-Greedy Sampling (DI-GS) techniques work best with ∼1.87% Euclidean Norm of Prediction Error (ENPE).

Scaling behavior of InAlN/GaN HEMTs on silicon for RF applications

Due to the low cost and the scaling capability of Si substrate, InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions. In this paper, a high-performance 50-nm-gate-length InAlN/GaN HEMT on Si with a high on/off current (Ion/Ioff) ratio of 7.28 × 106, an average subthreshold swing (SS) of 72 mV/dec, a low drain-induced barrier lowing (DIBL) of 88 mV, an off-state three-terminal breakdown voltage (BVds) of 36 V, a current/power gain cutoff frequency (fT/fmax) of 140/215 GHz, and a Johnson’s figure-of-merit (JFOM) of 5.04 THz V is simultaneously demonstrated. The device extrinsic and intrinsic parameters are extracted using equivalent circuit model, which is verified by the good agreement between simulated and measured S-parameter values. Then the scaling behavior of InAlN/GaN HEMTs on Si is predicted using the extracted extrinsic and intrinsic parameters of devices with different gate lengths (Lg). It presents that a fT/fmax of 230/327 GHz can be achieved when Lg scales down to 20 nm with the technology developed in the study, and an improved fT/fmax of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrown ohmic contact technology and 30% decreased parasitic capacitance. This study confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.

Normally-Off p-GaN Gate AlGaN/GaN Transistor with a New Schottky Second Gate

This study presents a normally-off dual-gate AlGaN/GaN high-electron-mobility transistor. The second gate is located between the p-GaN gate and the drain and is connected to the source. The optimized thickness and length of the AlGaN layer under the second gate next to the p-GaN significantly impact the maximum drain current and the off-state breakdown conditions. The reverse conduction characteristic is also improved because the freewheeling path of the reverse current is established between the second gate and the drain to prevent excessive voltage drop and conduction losses when the device is negatively biased. Compared with conventional HEMT, the proposed method shows a promising way to achieve normally-off GaN-based HEMTs with excellent forward ad reverse conduction performance.

Optimization of the Field Plate Design of a 1200 V p-GaN Power High-Electron-Mobility Transistor.

This study optimized the field plate (FP) design (i.e., the number and positions of FP layers) of p-GaN power high-electron-mobility transistors (HEMTs) on the basic of simulations conducted using the technology computer-aided design software of Silvaco. Devices with zero, two, and three FP layers were designed. The FP layers of the HEMTs dispersed the electric field between the gate and drain regions. The device with two FP layers exhibited a high off-state breakdown voltage of 1549 V because of the long distance between its first FP layer and the channel. The devices were subjected to high-temperature reverse bias and high-temperature gate bias measurements to examine their characteristics, which satisfied the reliability specifications of JEDEC.

Avalanche-like breakdown behavior of copolymer organic semiconductor-based Schottky junction structure

Organic field-effect transistors have demonstrated their outstanding off-state breakdown performance. Yet, the physical nature of their electric breakdown remains unexplored. In this paper, by employing a lateral back-to-back Schottky junction composed of diketopyrrolopyrrole-based conjugated copolymer (DPPT-TT) and Au metal, the breakdown performance of copolymer organic semiconductor (OSC) is experimentally demonstrated. The nondestructive/repeatable breakdown behavior and positive coefficient between temperature and breakdown voltage indicate that the avalanche-like breakdown mechanism plays a dominant role in determining the breakdown characteristic of OSC-based power devices. Based on the lateral back-to-back Schottky junction, a characterization method of key breakdown parameters is proposed. The extracted critical electric field (EC) of DPPT-TT is up to 5.0 MV/cm, which is more than one order of magnitude higher than that of single-crystal silicon. Despite the fact that copolymer OSCs are narrow bandgap semiconductors, they still deliver excellent breakdown performance, making them a promising building block for future power electronics.

High-performance vertical GaN field-effect transistor with an integrated self-adapted channel diode for reverse conduction

A vertical GaN field-effect transistor with an integrated self-adapted channel diode (CD-FET) is proposed to improve the reverse conduction performance. It features a channel diode (CD) formed between a trench source on the insulator and a P-type barrier layer (PBL), together with a P-shield layer under the trench gate. At forward conduction, the CD is pinched off due to depletion effects caused by both the PBL and the metal–insulator–semiconductor structure from the trench source, without influencing the on-state characteristic of the CD-FET. At reverse conduction, the depletion region narrows and thus the CD turns on to achieve a very low turn-on voltage (V F), preventing the inherent body diode from turning on. Meanwhile, the PBL and P-shield layer can modulate the electric field distribution to improve the off-state breakdown voltage (BV). Moreover, the P-shield not only shields the gate from a high electric field but also transforms part of C GD to C GS so as to significantly reduce the gate charge (Q GD), leading to a low switching loss (E switch). Consequently, the proposed CD-FET achieves a low V F of 1.65 V and a high BV of 1446 V, and V F, Q GD and E switch of the CD-FET are decreased by 49%, 55% and 80%, respectively, compared with those of a conventional metal–oxide–semiconductor field-effect transistor (MOSFET).

TCAD simulation of vertical diamond MISFET based on deep depletion characteristics with high current output capacity

A vertical diamond deep-depletion metal-insulator-semiconductor field-effect transistor (D3MISFET) with specific structural parameters and doping distribution is simulated in this paper. The vertical structure requires only p-type doping and has a lower on-resistance, which greatly improves the output capability of the transistor. The transfer characteristics, output characteristics and off-state breakdown characteristics of the vertical D3MISFET were given. The results show that the vertical D3MISFET has better output capability than the lateral-structure D3MISFET with the contribution of space charge transport limited current, and the output current can reach a high value of 700 mA/mm. An increase in temperature promotes a further increase in the output current of the device. The device switching ratio is greater than 109, and the breakdown voltage is 79 V.

Third quadrant overvoltage ruggedness of p-gate GaN HEMTs

Overvoltage ruggedness is an essential reliability requirement for non-avalanche AlGaN/GaN power devices against inductive transient spikes in the OFF-state breakdown events. In this work, we first report the 3rd-quadrant (i.e. source-to-drain reverse operation) overvoltage ruggedness of the p-gate GaN high-electron-mobility transistors (HEMTs) by performing static current–voltage (I–V) sweeps and dynamic unclamped inductive switching (UIS) experiments. Both experimental results reveal an inferior breakdown performance of the device under 3rd-quadrant blocking conditions, including a low static voltage of 57 V and a dynamic breakdown voltage (BV) of 155 V. In particular, this transient voltage is evidently degraded from 155 V to 114 V (i.e. a 26% reduction) by increasing the load current, which is significantly different from the stable BV (1.4 kV) achieved in the 1st-quadrant dynamic breakdown. Such unusual degradation behavior can be explained by the trapping-related carrier transport mechanism, which is supported by temperature-dependent breakdown characteristics. Further numerical simulations, de-capsulation failure analyses and repeated UIS experiments are carried out to study the failure mechanism and gain insight into the overvoltage capability of the device. These results suggest that the rational design of the p-gate GaN HEMTs with the desired 3rd-quadrant overvoltage ruggedness requires careful consideration, especially in reverse conduction events.

Novel Step Field Plate RF LDMOS Transistor for Improved BVDS-R on Tradeoff and RF Performance

In this article, a novel step field plate (SFP) laterally diffused metal–oxide–semiconductor (LDMOS) structure is proposed for improved breakdown voltage- ON resistance tradeoff and better RF performance. The proposed structure could be easily integrated into the CMOS process flow using four additional noncritical masks. The known materials like fully silicided polysilicon and silicon nitride (SiN) are used as FP and dielectric, respectively. The proposed design improves the device performance by uniformly distributing the electric field in the drift region. The higher drift doping for the same OFF-state breakdown voltage improves the ON resistance by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 2.5\times $ </tex-math></inline-formula> and ON-state breakdown voltage by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 2\times $ </tex-math></inline-formula> . Significant improvements in frequency behavior and flat power response are also observed. The device physics behind different observations are explained using detailed TCAD simulations.

Scalable Substrate Current Model for LDMOS Transistors Based on Internal Drain Voltage

In this work, a scalable robust substrate current model for laterally diffused MOS (LDMOS) transistors is presented. The model is created in two stages. First, a model for intrinsic drain voltage, which accurately captures the modulation of intrinsic drain voltage with applied gate and drain voltages, is developed. This model is then used to derive an expression for the substrate current. The accuracy of the substrate current model is verified by comparing it with the data measured from LDMOS transistors with different device dimensions. The model accurately captures the modulation of substrate current with bias voltages and shows excellent scalability. Different LDMOS designs are also suggested to reduce the substrate current at the same OFF-state breakdown voltage.

L G 55 nm T‐gate InGaN / GaN channel based high electron mobility transistors for stable transconductance operation

Nonlinearity operation and early gain suppression limit the high-frequency operation of GaN-HEMTs. Nonlinear transconductance and resistance drop-off at relatively large VGS are the major sources for the nonlinear operation of the high electron mobility transistors (HEMTs). In this article, we present the In0.1Ga0.9N channel-based HEMTs for stable transconductance operation. The device performance is evaluated for both Al0.3Ga0.7N, and In0.17Al0.83N barrier materials with silicon nitride passivation. The In0.17Al0.83N/In0.1Ga0.9N/GaN heterostructure device shows remarkable improvement in gate voltage swing than Al0.3Ga0.7N/In0.1Ga0.9N/GaN. LG 55 nm T-gate In0.17Al0.83N/In0.1Ga0.9N HEMT exhibited 5 A/mm of maximum drain current density (IDS, max) for 1 V gate bias, 0.72 S/mm of stable transconductance (gm,max), 43.5 V of off-state breakdown voltage (VBR), and 275/289 GHz of fT/fmax. The HEMT with AlGaN/InGaN/GaN heterostructure showed 2.81 A/mm of maximum drain current density for 1 V gate bias, 0.66 S/mm of stable transconductance, 55.3 V of VBR, and 252/263 GHz of fT/fmax. Moreover, a highest theoretical OIP3 value of 61.2 and 67.6 dBm obtained for AlGaN and InAlN barrier HEMTs, respectively. The proposed InGaN/GaN channel-based HEMTs are more reliable for high-frequency linear operation.

A Gradient Doped Integrated JFET With Improved Current Capability for HV Start-Up Circuit

The conventional high-voltage (HV) JFET (C-JFET) for HV start-up circuit suffers space charge modulation (SCM) effect especially when high current capability is required. Thus, the trade-off relationship between on-state breakdown voltage (ON-BV) and saturation current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Dsat</sub> ) is worthy of analysis. In this work, a gradient doped integrated HV junction field effect transistor (JFET) for HV start-up circuit with high ON-BV and high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Dsat</sub> is proposed. In the resistance region and drift region of the proposed JFET, different slot ratios of deep N-well (DNW) are adopted. Hence, the gradient doped drift region with adjusted injected current and concentration enhanced N-buffer region can be obtained without adding extra mask. Benefit by introducing the gradient doped structure, the dose of DNW can increase. The well- calibrated simulated results indicate that the proposed HV JFET with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$147~\mu $ </tex-math></inline-formula> m device length can obtain 889 V ON-BV and 929 V OFF-BV with 0.152 mA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m current capability, which is 21.6% better than our previously proposed D-JFET at the same off-state breakdown voltage level with the same device length.

Improved Performance of Fully-Recessed High-Threshold-Voltage GaN MIS-HEMT With in Situ H₂/N₂ Plasma Pretreatment

In this letter, we demonstrate a high-threshold-voltage and high-current-density normally-off SiN/AlN/ GaN-on-Si MIS-HEMT with <i>in situ</i> low-damage H₂/N₂ plasma pretreatment. The <i>in situ</i> plasma pretreatment was performed in a plasma enhanced atomic layer deposition (PEALD) system prior to the PEALD-AlN deposition, which effectively suppress the interface trap densities between the AlN/GaN interface and increase the mobility of electrons to 198.80 cm<inline-formula> <tex-math notation="LaTeX">$^{{2}}/\text {V} \cdot \text {s}$ </tex-math></inline-formula>. Therefore, the devices demonstrate state-of-art characteristics with a competitive maximum drain current of 683.75 mA/mm at <inline-formula> <tex-math notation="LaTeX">${V} _{\textit {GS}} =15\text{V}$ </tex-math></inline-formula> and a high threshold of 6.28 V. The devices also show ON/OFF current ratio of <inline-formula> <tex-math notation="LaTeX">$10^{{8}}$ </tex-math></inline-formula> and off-state breakdown voltage of 1778 V.

The effect of SiN x film for H plasma implantation in p-GaN/AlGaN/GaN high electron mobility transistors

A thin SiN x film was deposited on the p-GaN layer before H plasma implantation, which cause four orders of magnitude reduction in gate reverse leakage current. The OFF-state breakdown voltage increases by 89%. It displays a more stable dynamic performance. It is believed that the decrease of gate leakage current is attributed to the increase of trap activation energies in the p-GaN layer, It is concluded that improved dynamic characteristics are owing to the fact that the SiN x film blocks the excessive H plasma into the AlGaN barrier layer and reduces the implantation damage in AlGaN barrier layer.

Hole Injection Effect and Dynamic Characteristic Analysis of Normally Off p-GaN HEMT with AlGaN Cap Layer on Low-Resistivity SiC Substrate.

A p-GaN HEMT with an AlGaN cap layer was grown on a low resistance SiC substrate. The AlGaN cap layer had a wide band gap which can effectively suppress hole injection and improve gate reliability. In addition, we selected a 0° angle and low resistance SiC substrate which not only substantially reduced the number of lattice dislocation defects caused by the heterogeneous junction but also greatly reduced the overall cost. The device exhibited a favorable gate voltage swing of 18.5 V (@IGS = 1 mA/mm) and an off-state breakdown voltage of 763 V. The device dynamic characteristics and hole injection behavior were analyzed using a pulse measurement system, and Ron was found to increase and VTH to shift under the gate lag effect.