Off-state Breakdown Voltage Research Articles

Study on H plasma treatment enhanced p-GaN gate AlGaN/GaN HEMT with block layer

<sec>High electron mobility transistors(HEMTs)show tremendous potentials for high mobility, high breakdown voltage, low conduction, low power consumption, and occupy an important piece of the microelectronics field. The high-resistivity-cap-layer high electron mobility transistor (HRCL-HEMT) is a novel device structure. Based on the hole compensation mechanism, the p-GaN is converted into high resistance semiconductor material by hydrogen plasma implantation. Thus, the surface of the p-GaN layer will have a serious bombardment damage under the hydrogen plasma implantation. In practical work, it is also very challenging in the accurate controlling of the hydrogen injection rate, injection depth and injection uniformity. To achieve the required depth of injection, the injected hydrogen plasma is often more than the required dose or multiple injections times. The energy of hydrogen plasma plays a huge influence on the surface of the p-GaN layer.The leakage current will be generated on the device surface, which deteriorates the electrical performance of the device.</sec><sec>In this work, to protect the surface of p-GaN layer, a 2-nm Al<sub>2</sub>O<sub>3</sub> film is deposited on the surface of the p-GaN cap layer to reduce the implantation damage caused by hydrogen plasma treatment. The research shows that after the device deposited Al<sub>2</sub>O<sub>3</sub> film prior to the hydrogen plasma treatment, the gate reverse leakage current is reduced by an order of magnitude, the ratio of <i>I</i><sub>ON</sub> to <i>I</i><sub>OFF</sub> is increased by about 3 times. Meanwhile, the OFF-state breakdown voltage is increased from 410 V to 780 V. In addition, when the bias voltage is 400 V, the values of dynamic <i>R</i><sub>ON</sub> of devices A and B are 1.49 and 1.45 respectively, the device B shows a more stable dynamic performance. To analyze the gate leakage mechanism, a temperature-dependent current<i> I</i><sub>G</sub>-<i>V</i><sub>G</sub> testing is carried out, and it is found that the dominant mechanism of gate leakage current is two-dimensional variable range hopping (2D-VRH) at reverse gate voltage. The reason for reducing the gate reverse current is analyzed, and the Al<sub>2</sub>O<sub>3</sub> film increases the activation energy of trap level and changes the surface states of HR-GaN; furthermore, the Al<sub>2</sub>O<sub>3</sub> film blocks the injection of too much H plasma, thereby reducing the density of AlGaN barrier and channel trap states, and weakening the current collapse.</sec>

Correlation between sidewall surface states and off-state breakdown voltage of AlGaN/GaN HFETs

Correlation between the sidewall surface states and off-state breakdown voltage of AlGaN/GaN heterojunction field effect transistors (HFETs) is investigated for the first time. HFETs explored in this work were realized on a variety of isolation features including conventional mesa, non-slanted fin, and slanted fin. The output and transfer characteristics of the devices from all categories of the fabricated AlGaN/GaN HFETs were studied, and a link between the separation of isolation feature sidewalls in the drain access region and the breakdown voltage was observed. Simulation results showed that by shrinking the width of the isolation feature geometry, the peak of the electric field at the drain edge of the gate is reduced as a result of tailoring its profile when a more resistive path is imposed on the drain access region. While HFETs realized on fins of smaller width benefit more from the depleting effect of acceptor sidewall surface states and consequently a higher off-state breakdown voltage, they suffer from a lower current density in the on-state. The slanted fin isolation feature geometry that we proposed here, while maintaining high breakdown voltage in the off-state, reduces the resistance in the on-state, which is represented by its highest Baliga's figure of merit among the three categories of isolation feature geometries. The proposed solution for achieving an improvement to the off-state breakdown voltage of AlGaN/GaN HFETs relies on a technology that has already been explored as a successful alternative for the realization of enhancement-mode transistors (i.e., with positive threshold voltage).

Breakdown Voltage Enhancement of Al0.1Ga0.9 N Channel HEMT with Recessed Floating Field Plate

In this paper, electrical and microwave characteristics of Al0.1Ga0.9 N channel HEMTs was reported. The device performance were evaluated for conventional gate, field plate gate, and recessed floating field plate with Silicon nitride (SiN)/Hafnium oxide (HfO2) passivation. The recessed floating field plate HEMT with gate length LG = 0.8 μm, gate to drain distance LGD = 1 μm, and HfO2 (SiN) passivation HEMT reports peak drain current density (IDS) of 0.282(0.288) A/mm at VGS = 0 V, three terminal off-state breakdown voltage (VBR) of 677 (617) V, 6.38 Ω.mm of ON-resistance (RON), transconductance (gm,max) of 93(95) mS/mm, and FT/FMAX of 11.4/49 (12/22) GHz. The HfO2 (SiN) passivation device demonstrated the Johnson figure of merit (JFoM)) of 7.71 (7.404) THz.V and FMAX x VBR product of 33.173 (13.574) THz.V. The high JFoM along with high FMAX x VBR indicates the potential of the ultrawide bandgap AlGaN HEMTs for future power switching and high-power microwave applications. The breakdown voltage (VBR) of the floating field plate HEMT is improved 54 % from conventional HEMT and 31 % improvement from gate field plate HEMT.

Analytical breakdown voltage model for a partial SOI-LDMOS transistor with a buried oxide step structure

We have developed a simple physics-based two-dimensional analytical off-state breakdown voltage model of a partial buried oxide step structure (PBOSS) silicon-on-insulator laterally diffused metal oxide semiconductor (SOI-LDMOS) transistor. The analytical model includes the expressions of surface potential and electric field distributions in the drift region by solving the 2D Poisson equation. The electric field at the Si–SiO2 surface is modulated by additional electric field peaks developed due to the presence of the PBOSS structure. The uniformly distributed electric field results in improved breakdown voltage. Further, the breakdown voltage is analytically obtained by means of the critical electric field concept, to determine the breakdown characteristics. The model reveals the impact of the critical device design parameters such as thickness and length of the PBOSS structure, doping, and thickness of the drift region on the surface electric field and the breakdown voltage. The proposed model is verified by ATLAS two-dimensional simulations. The analytical model will be useful to design high-voltage SOI-LDMOS transistors for power switching applications.

Experimental Demonstration of Monolithic Bidirectional Switch With Anti-Paralleled Reverse Blocking p-GaN HEMTs

A monolithic bidirectional switch based on anti-paralleled two reverse blocking p-GaN HEMTs has been proposed and demonstrated in this work. The recessed Schottky drain technique is utilized to effectively reduce the on-state voltage and thus lowering the power loss of bidirectional switches. A significant reduction in parasitic elements and switch area is obtained by monolithic integration. The fabricated bidirectional switch exhibits a threshold voltage of ~1.85 V, on-state voltage of ~0.63 V, and the forward and reverse off-state breakdown voltages of ~650 V at I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S1-S2</sub> = 1 μA/mm. In addition, the function of proposed bidirectional switch as an AC power chopper has been successfully verified.

High performance GaN-based monolithic bidirectional switch using diode bridges

A p-GaN gate high electron mobility transistor (HEMT) based monolithic bidirectional switch with diode bridge structures is demonstrated. The bidirectional switch features four recessed anode Schottky barrier diodes embedded in a p-GaN HEMT, which effectively reduces the on-state voltage and minimizes the parasitic elements. The proposed device exhibits a high threshold voltage of 1.84 V, a low on-state voltage of 1.13 V, and a high forward and reverse off-state breakdown voltages of ∼1100 V. In addition, the function of the bidirectional switch as an AC power chopper is successfully verified.

Threshold Voltage Engineering of Enhancement-Mode AlGaN/GaN Metal-Oxide-Semiconductor High Electron Mobility Transistors with Different Doping Concentration of In Situ Cl− Doped Al2O3

This work used mist chemical vapor deposition to deposit an in situ Cl− doped Al2O3 film. 0.05 vol%, 0.1 vol%, and 0.15 vol% HCl were added to the precursor solutions for Cl− doping. The recess and Cl− doped Al2O3 gate dielectrics were used to form enhancement-mode AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors. The Cl− doping was confirmed by X-ray photoelectron spectroscopy and the negative charge concentration was extracted by capacitance-voltage method. It was found that the doping concentration affects the gate leakage performance and the carrier transportation mechanisms of the gate leakage were investigated. By using the Cl− doped Al2O3 as the gate dielectric layer, the device performance was improved, including more positive threshold voltage, higher output current at the same overdrive voltage, and over 600 V off-state breakdown voltage. In addition, the temperature-dependent threshold voltage characteristics were investigated to estimate the Cl− dopant runaway.

AlGaN/AlN/SiC Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors with Al2O3 Gate-Oxide and Step-Graded AlGaN Channel

Al0.75Ga0.25N/n-AlxGa1-xN/Al0.75Ga0.25N/AlN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs), grown on a SiC substrate, with step-graded Si-doped (n = 3 × 1018 cm-3) widegap AlxGa1-xN channel and Al2O3 gate-dielectric are investigated. Increased Al-compositions with x = 0.25, 0.5, and 0.75 towards the buffer were devised in the composite widegap channel. The high-k Al2O3 dielectric/passivation layer was grown by using a non-vacuum ultrasonic spray pyrolysis deposition (USPD) method. Experimental comparisons were made with respect to a conventional Schottky-gate HFET.The epitaxial structure of the studied Al2O3-dielectric Al0.75Ga0.25N/n-AlxGa1-xN/Al0.75Ga0.25N/AlN MOS-HFET (sample A) and Schottky-gate HFET (sample B). Both devices have the identical epitaxial structure grown on a SiC substrate by using a low-pressure metal-organic chemical vapor deposition (LP-MOCVD) system. The layer structure includes an undoped AlN buffer, a 20-nm undoped Al0.75Ga0.25N barrier, a 150-nm step-graded Si-doped (n = 3 × 1018 cm-3) AlxGa1-xN channel (x = 0.25, 0.5, and 0.75), and a 20-nm undoped Al0.75Ga0.25N barrier. Standard photolithography and lift-off techniques were used for device processing. For sample B, mesa etching was performed with respect to a 100-nm thick Ni barrier by using an inductively coupled-plasma reactive ion etcher (ICP-RIE). Flow rates were tuned and set at 10 sccm and 20 sccm for the mixed etching gases of BCl3 and Cl2, respectively. The 20-nm undoped Al0.75Ga0.25N barrier was etched away before deposition of source/drain electrodes. Ti (10 nm)/Al (50 nm)/Ni (10 nm)/Au (50 nm) were evaporated. The source/drain ohmic contacts were formed by annealing the sample for 25 seconds at 900°C by using a rapid thermal annealing (RTA) system (ULVAC MILA-5000). Then, 30-nm thick Al2O3 layer was deposited on the Al0.75Ga0.25N barrier by using the USPD technique. Finally, gate electrode of Ni (100 nm)/Au (50 nm) was evaporated after gate photolithography. As for sample A, the gate electrode was formed directly on the surface of Al0.75Ga0.25N barrier without oxide deposition.Improved device performance of the present MOS-HFET design have been obtained, including maximum drain-source current density (IDS, max ) of 130.1 A/mm at VGS = 10 V and VDS = 20 V, IDS at VGS = 0 V (IDSS0 ) of 83.1 mA/mm, on/off-current ratio (Ion /Ioff ) of 1.4 × 107, maximum extrinsic transconductance (gm, max ) of 11.8 mS/mm, two-terminal off-state gate-drain breakdown voltage (BVGD ) of -404 V, and three-terminal on-state drain-source breakdown voltage (BVDS ) of 364 V at 300 K. The present MOS-HFET design has also shown high spectral responsivity (SR) of 737 A/W under 250-nm deep-UV radiation at 300 K.

Improved on-state performance in AlGaN-channel heterojunction field-effect transistors with a quaternary AlGaInN barrier layer and a selectively grown n++-GaN contact layer

Al0.19Ga0.81N-channel metal-insulator-semiconductor heterojunction field-effect transistors (MIS-HFETs) with a quaternary AlGaInN barrier layer and a selectively regrown n++-GaN contact layer were fabricated using the self-alignment selective-area growth (SAG) technique. The self-alignment SAG process was accomplished by the local-area etching process and the subsequent refilling process with a highly-Si-doped n++-GaN layer by metalorganic chemical vapor deposition (MOCVD). It was confirmed that the ohmic contact resistance was drastically reduced from 10.5 Ωmm to 2.5 Ωmm via the self-alignment SAG contacts. Further, fabricated MIS-HFETs with a gate length of 1.5 μm and a drain-to-source length of 9.5 μm exhibited a high drain current density of over 300 mA/mm with a drain-to-source resistance of approximately 25 Ω mm. The fabricated devices also showed a high off-state breakdown voltage of 1220 V at a gate-to-drain length of 10 μm, corresponding to a breakdown field of 122 V/μm.

Simulation Study of A 1200V 4H-SiC Lateral MOSFET With Reduced Saturation Current

A 1200V 4H-SiC lateral double-diffused MOSFET (LDMOS) featuring a lightly doped P-top layer at the source side, and a high-doped N-well layer arranged between the channel and P-top layer is proposed. In order to promote the simulation accuracy, Sentaurus Process Tool that can simulate the oxidation, ion implantation, annealing, diffusion, etc. is used for structure establishment in this letter. In the ON-state, the electric potential at the end of the channel can be modulated and lowered due to the existence of P-top layer. The P-top layer can shield the voltage from the drain side, which results in the reduced saturation current ( $\text{I}_{\text {dsat}}$ ), especially at high drain-source voltage ( $\text{V}_{\text {DS}}$ ). The introduction of the N-well layer ensures that the P-top layer has almost no impact on the linear current ( $\text{I}_{\text {dlin}}$ ). Compared with the conventional SiC LDMOS, the $\text{I}_{\text {dsat}}$ at $\text{V}_{\text {DS}}\,\,=400\text{V}$ of the proposed LDMOS decreases by 24.2% with no degradation in the $\text{I}_{\text {dlin}}$ and the OFF-state breakdown voltage (BV). Benefiting from the suppressed $\text{I}_{\text {dsat}}$ , the proposed SiC LDMOS achieves a ON-state BV 366V higher than that of the conventional SiC LDMOS at the gate-source voltage of 20V. Since the short-circuit capability of the SiC power devices is much sensitive to the $\text{I}_{\text {dsat}}$ , the 24.2% reduction in $\text{I}_{\text {dsat}}$ can predict a considerable enhanced short-circuit capability. Simulation results show that the short-circuit withstand time can be improved by 105%.

AlN/GaN Superlattice Channel HEMTs on Silicon Substrate

High-electron-mobility transistor (HEMT) with AlN/GaN superlattice (SL) channel has been demonstrated on a silicon substrate. High OFF-state breakdown voltage ${V}_{\text {BR}}$ of 670 V (gate–drain spacing ${L}_{\text {GD}} = 8\,\,\mu \text{m}$ ) along with a maximum output current of 196 mA/mm, a channel electron total mobility of 507 cm2/ $\text{V}\cdot \text{s}$ , and an ON/ OFF ratio of over 107 was achieved in this novel HEMT. For the HEMT with ${L}_{\text {GD}} = 22\,\,\mu \text{m}$ , a high ${V}_{\text {BR}}$ of 1700 V was obtained with substrate floated. The influence of ${L}_{\text {GD}}$ , the gate–source voltage ${V}_{\text {GS}}$ , the isolated pattern, and substrate grounded and floated type was discussed to analyze the breakdown characteristics of HEMT. We investigated the trap states in the AlN/GaN SL channel of HEMTs by frequency-dependent capacitance and conductance measurements. A trap state density of $7.4\times 10^{{12}}$ – $1.2\times 10^{{13}}$ cm−2eV−1 is located at ${E}_{\text {T}}$ in a range of 0.29–0.33 eV of the main channel, while the trap state density in the parasitic channel decreases from $3.9\times 10^{{11}}$ cm−2eV−1 at an energy of 0.27 eV to $1.1\times 10^{{11}}$ cm−2eV−1 at an energy of 0.38 eV. The fabricated AlN/GaN SL channel HEMTs in this work reveal a great step toward the realization of the SL channel HEMTs on cost-effective silicon substrate and provide a novel technology for AlGaN multichannel devices to obtain high output current.

345-MW/cm² 2608-V NO₂ p-Type Doped Diamond MOSFETs With an Al₂O₃ Passivation Overlayer on Heteroepitaxial Diamond

Diamond metal oxide semiconductor field effect transistors (MOSFETs) on high-quality heteroepitaxial diamond (Kenzan diamond <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> ) with NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> p-type doping and an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> passivation overlayer exhibited a high off-state breakdown voltage of −2608 V. The 100-nm-thick Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> passivation overlayer on the hole channel increased the high-voltage-handling capability of the MOSFETs by substantially suppressing the off-state drain leakage currents. The MOSFET showed a specific on-resistance of 19.74 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a maximum drain current density of −288 mA/mm, with an extremely low gate leakage current <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ &lt; 10^{-{6}}$ </tex-math></inline-formula> mA/mm. The Baliga’s Figure-Of-Merits was experimentally determined to be 344.6 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the maximum DC power density was observed to be 21.0 W/mm.

The effect of high-k passivation layer on off-state breakdown voltage of AlGaAs/InGaAs HEMT

In this paper, the effects of different relative permittivity (εr) of the passivation layer on off-state breakdown voltage of AlGaAs/InGaAs HEMTs are analyzed by ISE-TCAD. It is shown that as εr value increases, the off-state breakdown voltage increases. When the εr value increased to 80, the off-state breakdown voltage increased from 17.23V to 24.13V by 40.9%. This is because the peak value of electric field at the proximity of gate edge is reduced with the increase of εr value and it can lead to the improvement of the off-state breakdown voltage of device. Meanwhile, the electric field peak value near the drain edge increases with the increase of the εr value, leading to an increase in the ionization probability of electron-hole ionization under the the grid-drain area. In addition, the results also show that the channel current (IDS) and transconductance (gm) of the device are slightly reduced by the passivation layer with a high εr value, while the specific channel on-resistance is hardly degraded. Therefore, the passivation layer with a high εr value can effectively improve the breakdown voltage of the device without sacrificing the DC characteristics of the device.

Improved Model on Buried-Oxide Damage Induced by Total-Ionizing-Dose Effect for HV SOI LDMOS

In this article, an improved model on buried-oxide (BOX) damage induced by total-ionizing-dose (TID) effect considering positive oxide trapped charge ( N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> ) generated in silicon on insulator (SOI)/BOX interface under negative electric field bias (field lines perpendicular to the SOI/BOX interface pointing from the top to the bottom of the BOX) and N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> saturation effect is proposed and adopted in accurate simulated analysis to predict the postirradiation device behavior. Moreover, the mechanism of high-voltage (HV) SOI lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) degradation during irradiation is also revealed by the proposed accurate simulation method. Tolerance design for radiation-hardened HV SOI LDMOS is discussed with the aid of the presented model. The tradeoff between postirradiation electrical characteristics and fresh electrical characteristics should be taken into account to meet the radiation hardening requirement. The radiation-hardened-by-design LDMOS introduced in this article keeps an OFF-state breakdown voltage above 120 V at D = 500 krad(Si) with operating voltage equal to 80 V, which is fabricated on a commercial SOI substrate material with plain interface quality parameters. The corresponding hardening strategy is also given.

An electronically programmable Off-State breakdown voltage in LDMOS transistor with dual-dummy-gate for high voltage ESD protection

A simulation study of the Off-State breakdown characteristics for a dual-dummy-gate SOI-LDMOS transistor is presented. The proposed device is a modification of a bulk-LDMOS transistor with a single dummy gate and two different diffused layers in the drift region. It introduces two additional dummy gates in the drift region, apart from the gate and extended drain electrode in the conventional device. The dummy gates need to be optimally biased to maximise the breakdown (VBR) and snapback voltages. 1D model modifying the 2D Poisson's equation has been proposed to analyse the 2D phenomena arising due to the perpendicular electric field originating from the dummy gate and extended-drain voltages and optimize the two dummy-gates bias. This approach provides an analytical solution for the Off-State VBR under the depletion condition. The model is verified with the TCAD simulations. The simulation results provide an insight into the electric field, potential distributions, and carrier concentrations in the drift region that characterizes the device performance. The impact ionization and current density contours are also included. It is found that the introduction of the two dummy gates enhances the maximum achievable VBR while it eliminates the need to have two different diffused regions that necessitate additional masks. Also, the proposed device has an intrinsic structural advantage of the reduced gate to drain capacitance due to the shielding effect of dummy gates. As the performance of the proposed device is controlled externally by the applied dummy gate voltage, the VBR is user programmable as per the requirement in electrostatic discharge (ESD) protection circuits for a sub-100 V application.

P-GaN Gated AlGaN/GaN E-mode HFET Fabricated with Selective GaN Etching Process

An O₂ based selective GaN etching process was developed herein for use in p-GaN gated AlGaN/GaN heterojunction field-effect transistor fabrication, where precise control of the p-GaN etching was an important process step that determined the device characteristics. The p-GaN layer was etched by a two-step process: low damage BCl₃/Cl₂ plasma etching in conjunction with Cl₂/N₂/O₂ based selective etching. A high selectivity of 53:1 for the p-GaN:AlGaN was achieved by the Cl₂/N₂/O₂ plasma etching. The device fabricated by the optimized etching process exhibited excellent enhancement-mode characteristics, i.e., a threshold voltage of 2.45 V, a specific on-resistance of 5.55 mΩ·cm², an on/off ratio of ~109, and an off-state breakdown voltage of >1100 V.

AlInGaN/GaN HEMTs With High Johnson’s Figure-of-Merit on Low Resistivity Silicon Substrate

This work demonstrates high-performance AlInGaN/AlN/GaN high electron mobility transistors grown on 150 mm p-type low resistivity (resistivity~ 20-100 Ω-cm) silicon substrate with state-of-the-art Johnson's figure-of-merit (JFOM). Current gain cut-off frequency (fT) of 83 GHz and 63 GHz and power gain cut-off frequency (fmax) of 95 GHz and 77 GHz with a three-terminal off-state breakdown voltage of 69 V and 127 V, resulting in a high JFOM of 5.7 THz-V and 8.1 THz-V are achieved on the devices with a gate length of 0.16 μm and gate to drain distance of 2 μm and 4 μm, respectively. The fT and J-FOM are comparable or better than the reported values obtained on high resistivity silicon and SiC substrates for devices with similar gate length. On the other hand, GaN-on-Si HEMT structure on the LR-Si substrate exhibits lower power gain and power added efficiency due to strong capacitive coupling effects. TCAD large signal output power simulation indicates significant improvements in output power by minimizing the defects and free charge carriers in the GaN buffer even in the presence of the parasitic channel conduction and conductive silicon substrate. We further propose a modified equivalent circuit model of the parasitic conduction to take into account the conductivity of the GaN and AlGaN buffer.

Influence of doping profile of GaN:Fe buffer layer on the properties of AlGaN/AlN/GaN heterostructures for high-electron mobility transistors

The effect of the Fe doping profile of the GaN buffer layer in the heterostructures for high-electron mobility transistors was studied experimentally and by computer simulation. The exponential Fe tail extending to the nominally undoped layers may greatly affect the properties of the structure. Reducing the distance between the channel and the Fe-doped buffer to less than 1 μm results in a decrease in the density and mobility of the two-dimensional electron gas. It also leads to the higher off-state avalanche breakdown voltage and reduced leakage current. A good agreement between simulation and experimental data is obtained when taking into account a Fe segregation effect, while an abrupt doping profile lead to significant discrepancies between them

Improving Off-State Breakdown Voltage of a Double-Channel AlGaN/GaN HEMT with Air-Bridge Field Plate and Slant Field Plate

The off-state breakdown voltage of a double-channel AlGaN/GaN HEMT is improved by employing an air-bridge field plate (AFP) and a slant field plate at the gate electrode. It has been observed that using the AFP only can reduce the peak electric field under the gate edge to a certain extent, and a slant field plate can be added to obtain an even better result. The breakdown voltage is increased from 19 V of the initial structure to 200 V of the optimized structure.

Deep-Recessed β-Ga₂O₃ Delta-Doped Field-Effect Transistors With In Situ Epitaxial Passivation

We introduce a deep-recessed gate architecture in β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> delta-doped field-effect transistors (FETs) for improvement in dispersion and breakdown properties. The device design incorporates an unintentionally doped (UID) β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> layer as the passivation dielectric. To fabricate the device, the deep-recess geometry was developed using BCl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> plasma-based etching at 5 W reactive ion etching (RIE) power to ensure minimal plasma damage. Etch damage incurred with plasma etching was mitigated by annealing in vacuum at temperatures above 600 °C. A gate-connected field-plate edge termination was implemented for efficient field management. Negligible surface dispersion with lower knee walkout at high VDS, and better breakdown characteristics compared to their unpassivated counterparts were achieved. A three-terminal OFF-state breakdown voltage of 315 V, corresponding to an average breakdown field of 2.3 MV/cm was measured. The device breakdown was limited by the field-plate/passivation edge and presents scope for further improvement. This demonstration of epitaxially passivated FET is a significant step for β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> technology since the structure simultaneously provides control of surface-related dispersion and excellent field management.