Off-detector Electronics Research Articles

Development of the ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

Following new Trigger and Data AcQuisition (TDAQ) buffering and rate requirements as well as the high radiation doses and the pileup conditions of the High-Luminosity LHC, the ATLAS Liquid Argon Calorimeter electronics will be upgraded to readout the 182,500 calorimeter cells at 40 MHz with 16 bit dynamic range. The triangular calorimeter signals are amplified and shaped by the analogue electronics over a dynamic range of 16 bits, with low noise and excellent linearity. Developments of low-power preamplifiers and shapers to meet these requirements are ongoing in CMOS 130 nm. In order to digitize the analogue signals on two gains after shaping, radiation-hard, low-power 40 MHz 14-bit ADCs are developed using a SAR architecture in 65 nm CMOS. Characterization of the first prototypes of the Front-End components show good promise to fulfill all the requirements. The signals will be sent at 40 MHz to the off-detector electronics, that will make use of FPGAs connected through high-speed links to perform energy and time reconstruction through the application of digital filtering and appropriate corrections. Reduced data are sent with low latency to the first level trigger, while the full data are buffered until the reception of trigger accept signals. The data-processing, control and timing functions will be realized by dedicated boards connected through ATCA crates. Results of tests of the first prototypes of Front-End components will be presented, along with design studies on the performance of the off-detector readout system.

RPC upgrade project for CMS Phase II

The Muon Upgrade Phase II of the Compact Muon Solenoid (CMS) aims to guarantee the optimal conditions of the present system and extend the η coverage to ensure a reliable system for the High Luminosity Large Hadron Collider (HL-LHC) period. The Resistive Plate Chambers (RPCs) system will upgrade the off-detector electronics (called link system) of the chambers currently installed chambers and place improved RPCs (iRPCs) to cover the high pseudo−rapidity region, a challenging region for muon reconstruction in terms of background and momentum resolution. In order to find the best option for the iRPCs, an R&D program for new detectors was performed and real size prototypes have been tested in the Gamma Irradiation Facility (GIF++) at CERN. The results indicated that the technology suitable for the high background conditions is based on High Pressure Laminate (HPL) double-gap RPC. The RPC Upgrade Phase II program is planned to be ready after the Long Shutdown 3 (LS3).

Phase I Upgrade of the Readout System of the Vertex Detector at the LHCb Experiment

This article describes the high-speed system designed to meet the challenging requirements for the readout of the new pixel VErtex LOcator (VELO) of the upgraded LHCb experiment. All elements of the electronics readout chain will be renewed to cope with the requirement of ~40-MHz full-event readout rate. The pixel sensors will be equipped with VeloPix ASICs and placed at ~5 mm from the Large Hadron Collider (LHC) beams in a secondary vacuum tank in an extremely high and nonhomogeneous radiation environment. The front-end (FE) ASICs with the highest occupancy will have to cope with pixel-hit rates above ~900 Mhits/s using up to four 5.13-Gb/s data readout links. Each module comprises six VeloPix ASICs, wire-bonded to two FE hybrid boards, while a third hybrid will employ a GBTx ASIC as the control interface. High-speed data will reach the wall of the vacuum chamber through low-mass flexible copper tapes. A custom board routes the signals outside the vacuum tank. On the air side, an optical and power board converts the electrical high-speed signals into optical signals for transmission from the underground cavern to the off-detector electronics that process data and send them to a farm of computers for further analysis. Several tests allowing the validation of the system are described here with special emphasis on a test with proton beams that confirms the correct operation of the whole readout hardware.

The PreProcessor module for the ATLAS Tile Calorimeter at the HL-LHC

The Tile Calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC). In 2026, the LHC will be upgraded to the High Luminosity LHC (HL-LHC) allowing it to deliver up to 7 times the nominal instantaneous design luminosity. The Phase-II TileCal Upgrade will accommodate the detector and data acquisition system to the HL-LHC requirements. The on- and off-detector electronics will be completely redesigned using a new readout architecture with a full-digital trigger system. The upgraded on-detector electronics will transfer digitized data for every bunch crossing (∼25 ns) to the Tile PreProcessor system in the counting rooms, requiring a total data bandwidth of 40 Tbps. The TilePPr will store the detector data in pipeline memories to meet the new ATLAS Trigger and Data Acquisition architecture requirements, and will interface with the FELIX system and the first level trigger system.

A New Interface Board for the Level-1 Muon Barrel Trigger Upgrade of the ATLAS Experiment

The Level-1 barrel trigger of the ATLAS experiment is based on the resistive plate chambers (RPCs) detectors. The on-detector trigger electronics identifies muons with specific values of transverse momentum, by using coincidences between different layers of detectors. Trigger data are then transferred from on-detector to off-detector trigger electronics boards. Data are processed by a complex system, which combines trigger data from the barrel and the end-cap regions and provide the combined muon candidate to the central trigger processor (CTP). The system has been performing well for almost a decade. However, in order to cope with continuously increasing large hadron collider luminosity and more demanding requirements on trigger efficiency and performance, various upgrades for the full-trigger system were already deployed and others are foreseen in the next years. Most of the trigger upgrades are based on the state-of-the-art technologies and allow designing more complex trigger menus, increasing processing power and data transfer bandwidth in order to send more trigger candidates, to perform topological selections, and to support new physics studies. In this paper, we describe the design of the first prototype of the barrel interface board, designed around a Xilinx field-programmable gate array, which transfers RPC trigger data to the CTP system; the board supports the optical transmission of trigger data with fixed latency and new trigger algorithms. We discuss the design strategies, the hardware implementation, and the results of the first functional and integration tests.

The CMS ECAL Phase-2 upgrade for high precision energy and timing measurements

The CMS electromagnetic calorimeter (ECAL) is a homogeneous calorimeter made of about 75,000 lead tungstate scintillating crystals. In view of the high-luminosity phase of the LHC, the ECAL electronics must be upgraded to cope with the more stringent requirements in terms of trigger latency and rate. The new electronics will transmit the data in streaming mode from the front-end electronics to the off-detector electronics, where the trigger primitives will be formed in powerful FPGAs. The front-end electronics will feature two new radiation-hard chips: a dual gain trans-impedance amplifier (TIA) and a sampling ADC with loss-less data compression. The TIA choice preserves the fast pulse shape of signals in the lead tungstate coupled to avalanche photodiodes (APD), and it is more resilient to the noise increase due to the radiation-induced APD leakage current. An important characteristic of the new design will be the capability to provide precision timing measurements, of the order of 30ps, for photons and electrons above 50GeV. The excellent time resolution will improve the overall CMS physics performance by mitigating the high pile-up effects. First characterization results of the TIA chip will be shown, and studies of energy and timing resolution performed in beam tests with the prototype electronics will be presented.

Simulation of the CMS electromagnetic calorimeter response at the energy and intensity frontier

The electromagnetic calorimeter (ECAL) of the CMS experiment at the LHC is a homogeneous calorimeter made of 75848 lead tungstate (PbWO4) scintillating crystals, designed for high precision electron and photon energy measurements in hadron collisions at the TeV scale. The detailed simulation of the calorimeter response is crucial for physics analyses involving electrons, photons, jets or missing energy. The detector simulation has been tuned during the first LHC run, including a detailed description of the upstream material. The increase of centre-of-mass energy, bunch crossing rate and instantaneous luminosity in the second run has resulted in updated and improved data readout, settings and reconstruction techniques. Furthermore, aging effects due to radiation, in particular increases in noise in the photodetectors and crystal transparency losses, have caused a change of the calorimeter response. All of these effects have been taken into account in order to improve the simulation of the calorimeter response and to ensure that it describes the data well over time, notwithstanding the evolving conditions. In 2024 the ECAL will undergo an upgrade to cope with the high luminosity phase of the LHC (HL-LHC). The temperature of the calorimeter will be lowered to mitigate the aging effects, the front-end electronics will be replaced with a faster version and the data will be read out in streaming mode towards the off-detector electronics. The fast PbWO4 response time will be exploited to measure the timing of high-energy showers with high precision. A detailed simulation description of the crystal response is fundamental for the design of the detector electronics and to predict the performance for the energy and timing measurements. The techniques employed in tuning the simulation of the detector response for the present running conditions and for the upgrade will be presented.

Data Acquisition and Software for the ATLAS Tile Calorimeter Phase-II Upgrade Demonstrator

After a series of upgrades, the High Luminosity LHC (HL-LHC) will have an instantaneous luminosity of 5-7 times larger than the LHC design value. The readout electronics of the ATLAS Tile Calorimeter (TileCal) will undergo a substantial upgrade during the Phase-II upgrade to accommodate the HL-LHC requirements. After the Phase-II upgrade, the TileCal detector signals will be digitized by on-detector electronics and transferred to the the TileCal PreProcessors (TilePPr), which is a part of the off-detector electronics. In the TilePPr, the digitized data will be stored in pipeline buffers and be packed and readout to the Front-End Link eXchange (FELIX) system upon receiving a trigger decision. At the same time, the energy information will be reconstructed from the detector data and transferred to the Level-1 Calorimeter Trigger (L1Calo) system in different granularity for every bunch crossing. The TileCal Demonstrator is designed to evaluate the performance of the TileCal with new readout electronics without compromising the present data taking. This contribution describes in detail the data processing and the hardware, firmware, software components of the TileCal Demonstrator system, together with the results of beam tests performed at CERN.

Self-contained configuration scrubbing in Xilinx FPGAs for on-detector applications

Off-detector electronics in trigger and data acquisition systems of High-Energy Physics experiments is often implemented by means of SRAM-based Field Programmable Gate Arrays, due their high-performance in real-time data processing and transfer. The usage of such devices on detector is mostly limited by their sensitivity to radiation-induced upsets in the configuration. In this work, we describe a soft core for correcting these effects in Xilinx devices. The core does not require any external memory for hosting the golden configuration, yet it is able to correct the configuration of an assigned design and its own configuration. In order to prove the effectiveness of our solution, we report results from 62-MeV proton irradiation tests at the INFN Laboratori Nazionali del Sud (Catania, Italy).

The Phase-2 electronics upgrade of the ATLAS liquid argon calorimeter system

The LHC high-luminosity upgrade in 2024–2026 requires the associated detectors to operate at luminosities about 5–7 times larger than assumed in their original design. The pile-up is expected to increase to up to 200 events per proton bunch-crossing. The current readout of the ATLAS liquid argon calorimeters does not provide sufficient buffering and bandwidth capabilities to accommodate the hardware triggers requirements imposed by these harsh conditions. Furthermore, the expected total radiation doses are beyond the qualification range of the current front-end electronics. For these reasons an almost complete replacement of the front-end and off-detector readout system is foreseen for the 182,468 readout channels. The new readout system will be based on a free-running architecture, where calorimeter signals are amplified, shaped and digitized by on-detector electronics, then sent at 40 MHz to the off-detector electronics for further processing. Results from the design studies on the performance of the components of the readout system are presented, as well as the results of the tests of the first prototypes.

Electronics and triggering challenges for the CMS High Granularity Calorimeter

The High Granularity Calorimeter (HGCAL), presently being designed by the CMS collaboration to replace the CMS endcap calorimeters for the High Luminosity phase of LHC, will feature six million channels distributed over 52 longitudinal layers. The requirements for the front-end electronics are extremely challenging, including high dynamic range (0.2 fC–10 pC), low noise (∼2000 e− to be able to calibrate on single minimum ionising particles throughout the detector lifetime) and low power consumption (∼20 mW/channel), as well as the need to select and transmit trigger information with a high granularity. Exploiting the intrinsic precision-timing capabilities of silicon sensors also requires careful design of the front-end electronics as well as the whole system, particularly clock distribution. The harsh radiation environment and requirement to keep the whole detector as dense as possible will require novel solutions to the on-detector electronics layout. Processing the data from the HGCAL imposes equally large challenges on the off-detector electronics, both for the hardware and incorporated algorithms. We present an overview of the complete electronics architecture, as well as the performance of prototype components and algorithms.

Upgrade of the ATLAS Hadronic Tile Calorimeter for the High Luminosity LHC

The Large Hadron Collider (LHC) has envisaged a series of upgrades towards a High Luminosity LHC (HL-LHC) delivering five times the LHC nominal instantaneous luminosity. The ATLAS Phase II upgrade, in 2024, will accommodate the upgrade of the detector and data acquisition system for the HL-LHC. The Tile Calorimeter (TileCal) will undergo a major replacement of its on- and off-detector electronics. In the new architecture, all signals will be digitized and then transferred directly to the off-detector electronics, where the signals will be reconstructed, stored, and sent to the first level of trigger at the rate of 40 MHz. This will provide better precision of the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. Changes to the electronics will also contribute to the reliability and redundancy of the system. Three different front-end options are presently being investigated for the upgrade, two of them based on ASICs, and a final solution will be chosen after extensive laboratory and test beam studies that are in progress. A hybrid demonstrator module is being developed using the new electronics while conserving compatibility with the current system. The status of the developments will be presented, including results from the several tests with particle beams.

Upgrade of Tile Calorimeter of the ATLAS Detector for the High Luminosity LHC.

The Tile Calorimeter (TileCal) is the hadronic calorimeter of ATLAS covering the central region of the ATLAS experiment. TileCal is a sampling calorimeter with steel as absorber and scintillators as active medium. The scintillators are read out by wavelength shifting fibers coupled to photomultiplier tubes (PMT). The analogue signals from the PMTs are amplified, shaped and digitized by sampling the signal every 25 ns. The High Luminosity Large Hadron Collider (HL-LHC) will have a peak luminosity of 5 × 1034 cm −2 s −1, five times higher than the design luminosity of the LHC. TileCal will undergo a major replacement of its on- and off-detector electronics for the high luminosity programme of the LHC in 2026. The calorimeter signals will be digitized and sent directly to the off-detector electronics, where the signals are reconstructed and shipped to the first level of trigger at a rate of 40 MHz. This will provide a better precision of the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. Three different options are presently being investigated for the front-end electronic upgrade. Extensive test beam studies will determine which option will be selected. Field Programmable Gate Arrays (FPGAs) are extensively used for the logic functions of the off- and on-detector electronics. One hybrid demonstrator prototype module with the new calorimeter module electronics, but still compatible with the present system, may be inserted in ATLAS at the end of 2016.

Upgrade of the ATLAS hadronic Tile Calorimeter for the High luminosity LHC

The Tile Calorimeter (TileCal) is the hadronic calorimeter of ATLAS covering the central region of the ATLAS experiment. TileCal is a sampling calorimeter with steel as absorber and scintillators as active medium. The scintillators are read out by wavelength shifting fibers coupled to photomultiplier tubes (PMT). The analogue signals from the PMTs are amplified, shaped and digitized by sampling the signal every 25 ns. The High Luminosity Large Hadron Collider (HL-LHC) will have a peak luminosity of 5 × 1034 cm−2s−1, five times higher than the design luminosity of the LHC . TileCal will undergo a major replacement of its on- and off-detector electronics for the high luminosity programme of the LHC starting in 2026. All signals will be digitized and then transferred directly to the off-detector electronics, where the signals will be reconstructed, stored, and sent to the first level of trigger at a rate of 40 MHz. This will provide better precision of the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. Changes to the electronics will also contribute to the reliability and redundancy of the system. Three different front-end options are presently being investigated for the upgrade and a final solution will be chosen after extensive laboratory and test beam studies that are in progress. A hybrid demonstrator module was developed using the new electronics while conserving compatibility with the current system. The demonstrator undergoes extensive testing and will be installed in ATLAS during one of the next winter maintenance periods.

A custom readout electronics for the BESIII CGEM detector

For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM readout, and reviewing the first silicon results of the chip prototype.

Optimization on fixed low latency implementation of the GBT core in FPGA

In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

Performance of the ATLAS Hadronic Tile Calorimeter in Run-2 and its Upgrade for the High Luminosity LHC

The Tile Calorimeter (TileCal) of the ATLAS experiment at the LHC is the central hadronic calorimeter designed for energy reconstruction of hadrons, jets, tauparticles and missing transverse energy. TileCal is a scintillator-steel sampling calorimeter and it covers the region of pseudo-rapidity up to 1.7, with almost 10000 channels measuring energies ranging from ∼30 MeV to ∼2 TeV. Each stage of the signal production, from scintillation light to the signal reconstruction, is monitored and calibrated. The performance of the Tile calorimeter has been studied in-situ employing cosmic ray muons and a large sample of proton-proton collisions, acquired during the operations of the LHC. Prompt isolated muons of high momentum from electroweak bosons decays are employed to study the energy response of the calorimeter at the electromagnetic scale. The calorimeter response to hadronic particles is evaluated with a sample of isolated hadrons. The modelling of the response by the Monte Carlo simulation is discussed. The calorimeter timing calibration and resolutions are studied with a sample of multijets events. Results on the calorimeter operation and performance are presented, including the calibration, stability, absolute energy scale, uniformity and time resolution. TileCal performance satisfies the design requirements and has provided an essential contribution to physics results in ATLAS.The Large Hadron Collider (LHC) has envisaged a series of upgrades towards a High Luminosity LHC (HL-LHC), delivering five times the LHC nominal instantaneous luminosity. The ATLAS Phase II upgrade, in 2024, will accommodate the detector and data acquisition system for the HL-LHC. In particular, the Tile Calorimeter will undergo a major replacement of its on- and off-detector electronics. All signals will be digitised and then transferred directly to the off-detector electronics, where the signals will be reconstructed, stored, and sent to the first level of trigger at a rate of 40 MHz. This will provide better precision for the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. Changes to the electronics will also contribute to the reliability and redundancy of the system. Three different front-end options are presently being investigated for the upgrade. Results of extensive laboratory tests and with beams of the three options will be presented, as well as the latest results on the development of the power distribution and the off-detector electronics.

Upgrade of the ATLAS Tile hadronic calorimeter for high-luminosity LHC run

The ATLAS Tile Calorimeter (TileCal) will undergo a major replacement of its on- and off-detector electronics for the Long Shutdown 3 that is planned for 2024 and 2025. All signals will be digitised and transferred directly to the off-detector electronics, where the signals are reconstructed, stored, and sent to the first level of trigger at a rate of 40MHz. This will provide better precision of the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. Changes to the electronics will also contribute to the reliability and redundancy of the system. Three different front-end options are presently being investigated for the upgrade and will be chosen after extensive test beam studies. A Hybrid Demonstrator module has been developed. The demonstrator is undergoing extensive testing and is planned for insertion in ATLAS.

Upgrade of the ATLAS Tile Calorimeter Electronics

The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the central region of the ATLAS experiment at LHC. The TileCal readout consists of 9852 channels. The bulk of its upgrade will occur for the High Luminosity LHC phase (Phase II) where the peak luminosity will increase 5× compared to the design luminosity (1034 cm-2s-1) at center of mass energy of 14 TeV. The TileCal upgrade aims at replacing the majority of the on- and off-detector electronics to the extent that all calorimeter signals will be digitized and sent to the off-detector electronics in the counting room. To achieve the required reliability, redundancy has been introduced at different levels. Three different options are presently being investigated for the front-end electronic upgrade. Extensive test beam studies will determine which option will be selected. 10.24 Gbps optical links are used to read out all digitized data to the counting room while 4.8 Gbps down-links are used for synchronization, configuration and detector control. For the off-detector electronics a pre-processor (sROD) is being developed, which takes care of the initial trigger processing while temporarily storing the main data flow in pipeline and de-randomizer memories. Field Programmable Gate Arrays are extensively used for the logic functions off- and on-detector. One demonstrator prototype module with the new calorimeter module electronics, but still compatible with the present system, is planned to be inserted in ATLAS at the end of 2015.

Development of a high data-throughput ADC board for the PROMETEO portable test-bench for the upgraded front-end electronics of the ATLAS TileCal

The Large Hadron Collider (LHC) is preparing for a major Phase-II upgrade scheduled for 2022 [1]. The upgrade will require a complete redesign of both on- and off-detector electronics systems in the ATLAS Tile hadron Calorimeter (TileCal) [2]. The PROMETEO (A Portable ReadOut ModulE for Tilecal ElectrOnics) stand-alone test-bench system is currently in development and will be used for the certification and quality checks of the new front- end electronics. The Prometeo is designed to read in digitized samples from 12 channels simultaneously at the bunch crossing frequency while accessing quality of information in realtime. The main board used for the design is a Xilinx VC707 evaluation board with a dual QSFP+ FMC (FPGA Mezzanine Card) module for read-out and control of the front-end electronics. All other functions are provided by a HV board, LED board and a 16 channel ADC daughter board. The paper relates to the development and testing of the ADC board that will be used in the new Prometeo system.