Abstract

The ATLAS Tile Calorimeter (TileCal) will undergo a major replacement of its on- and off-detector electronics for the Long Shutdown 3 that is planned for 2024 and 2025. All signals will be digitised and transferred directly to the off-detector electronics, where the signals are reconstructed, stored, and sent to the first level of trigger at a rate of 40MHz. This will provide better precision of the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. Changes to the electronics will also contribute to the reliability and redundancy of the system. Three different front-end options are presently being investigated for the upgrade and will be chosen after extensive test beam studies. A Hybrid Demonstrator module has been developed. The demonstrator is undergoing extensive testing and is planned for insertion in ATLAS.

Highlights

  • The ATLAS Tile Calorimeter (TileCal) will undergo a major replacement of its on- and off-detector electronics for the Long Shutdown 3 that is planned for 2024 and 2025

  • Wave-Length Shifting (WLS) fibres are coupled to each tile cell to collect the produced light and are readout by photomultiplier tubes (PMT) located inside mechanical supports called drawers

  • The current ATLAS electronics are coming to the end of their design lifespan and with the new HL-Large Hadron Collider (LHC) design requirements there is a need for a complete replacement and redesign of both the on- and off-detector electronics of the ATLAS TileCal [3]

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Summary

The Tile Calorimeter

The TileCal is the central hadronic calorimeter within the ATLAS detector (Figure 1) at the Large Hadron Collider (LHC) situated at CERN, Geneva [1]. The TileCal is composed of four barrel sections (two central and two extended barrels), each containing 64 azimuthal slices. There are more than 5000 tile cells, each being readout by two PMTs. Drawers are found within the outer section of each TileCal slice, drawers contain the on-detector electronics. An analog sum of the processed signal of several PMTs serves as input to the level 1 (L1) trigger. Signals from the PMTs are shaped, amplified and digitised with a 10 bit ADC at 40 MHz and are stored in temporary pipeline memories on-detector while they wait for the L1 acceptance trigger

Upgrade Motivation and requirements
Current electronics
Electronics Upgrade
TilePPr
Hybrid demonstrator
Conclusion
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