Off-axis Si Research Articles

Effect of N and Al Doping on 3C-SiC Stacking Faults

This study offers a comprehensive examination of the behavior of 3C-SiC crystals grown on 4° off-axis (100) Si substrates with different off-axis angles along <110> and <100> for N and Al doping, respectively. The investigation takes advantage of molten KOH etching to conduct an in-depth investigation of the average density and size of the SFs inside the crystal for both n- and p-type doped 3C-SiC epitaxial layers. Moreover, 3C-SiC grown on a <100> off-cut substrate was revealed to have a greater concentration of SFs due to the absence of self-annihilation along the plane (-1-10). Considering two different doping ranges suitable for IGBTs and MOSFETs development, the impact of doping and off-angle on the crystal quality, concentration, and length distribution of SFs was then investigated in order to quantify the influence of N and Al incorporation on the structural and optical characteristics of the semiconductor. It turned out that under heavy nitrogen doping (~1019 cm-3), when the dopant concentration grew, the average length of the stacking faults (SFs) expanded while their density dropped.

Effect of Nitrogen and Aluminum Doping on 3C-SiC Heteroepitaxial Layers Grown on 4° Off-Axis Si (100).

This work provides a comprehensive investigation of nitrogen and aluminum doping and its consequences for the physical properties of 3C-SiC. Free-standing 3C-SiC heteroepitaxial layers, intentionally doped with nitrogen or aluminum, were grown on Si (100) substrate with different 4° off-axis in a horizontal hot-wall chemical vapor deposition (CVD) reactor. The Si substrate was melted inside the CVD chamber, followed by the growth process. Micro-Raman, photoluminescence (PL) and stacking fault evaluation through molten KOH etching were performed on different doped samples. Then, the role of the doping and of the cut angle on the quality, density and length distribution of the stacking faults was studied, in order to estimate the influence of N and Al incorporation on the morphological and optical properties of the material. In particular, for both types of doping, it was observed that as the dopant concentration increased, the average length of the stacking faults (SFs) increased and their density decreased.

Effect of a SiC seed layer grown at different temperatures on SiC film deposition on top of an AlN/Si(110) substrate

We have formed silicon carbide (SiC) seed layers at various substrate temperatures by ultralow-pressure chemical vapor deposition using monomethylsilane (CH3SiH3) on aluminum nitride (AlN) films grown on off-axis Si(110) substrates. After that, we grew SiC films on the seed layers by pulsed laser deposition using a SiC target. We investigated the effects of the seed layers formed at various temperatures on the crystallinity and surface morphology of the SiC films thereon. The SiC films grown on the seed layers tended to have lower surface roughnesses than the film grown directly on the AlN film. The SiC film grown on the seed layer formed at 600 °C on the AlN film had the best crystallinity among the films. The formation of the seed layers had an effect on the relaxation of the internal stress in the SiC films. The SiC film can be used to grow epitaxial graphene by high-temperature annealing, and the AlN layer on Si plays a role in insulating graphene devices from the Si substrate. Therefore, the graphene transistors are one of the possible applications for epitaxial graphene grown on SiC/AlN/Si.

Evidence of Channel Mobility Anisotropy on 4H-SiC MOSFETs with Low Interface Trap Density

In this work, we have evaluated 4° off-axis Si face 4H-SiC MOSFETs channel performance along both the [11-20] (perpendicular to steps) and [1-100] (parallel to steps) orientations, to evidence possible anisotropy on Si-face due to roughness scattering effect. Improved gate oxide treatments, allowing low interface state densities and therefore high mobility values, have been used on both NO and N2O annealed gate oxides. With these high channel mobility samples, a small anisotropy effect (up to 10%) can be observed at high electric fields. The anisotropy can be seen both at room and high temperatures. However, the optical phonon scattering is the dominant effect under these biasing conditions.

Growth of 3C-SiC(111) on AlN/off-axis Si(110) hetero-structure and formation of epitaxial graphene thereon

A cubic silicon carbide (3C-SiC) film was fabricated by pulsed laser deposition on an aluminum nitride layer grown on an off-axis Si(110) substrate. This is the first report about the use of off-axis Si(110) substrates for manufacturing SiC/AlN/Si multilayers. A high-quality epitaxial 3C-SiC(111) film without rotation domains or twins, as evidenced by reflection high-energy electron diffraction (RHEED) measurements, was successfully obtained by using a wurtzite AlN(0001)/off-axis Si(110) substrate. On this 3C-SiC film, graphene was formed through annealing in ultrahigh vacuum at 1200 °C and its structure and chemical bonding were investigated via in situ RHEED and X-ray photoelectron spectroscopy; the full width at half maximum of the C 1s core level peak and the root-mean-square surface roughness were 0.60 eV and 0.14 nm, respectively, which were substantially lower than those (0.73 eV and 1.44 nm) previously reported for a graphene sample with similar thickness but formed on a SiC/AlN/on-axis Si(110) substrate.

GaN epitaxial growth on 4 degree off-axis Si- and C-face 4H-SiC without buffer layers by tri-halide vapor-phase epitaxy with high-speed wafer rotation

The results of GaN epitaxial crystal growth on 4° off-axis Si- and C-face 4H-SiC without buffer layers by tri-halide vapor-phase epitaxy (THVPE) with high-speed wafer rotation and the properties of the obtained material are briefly described in this paper. GaN epitaxial layers were grown on 4° off-axis 4H-SiC(0001)Si and 4H-SiC(000-1)C substrates. The obtained material’s properties were studied by Nomarski optical microscopy, scanning electron microscopy, photoluminescence, surface two-photon excitation microscopy, X-ray diffraction and Raman spectroscopy. The structural and optical properties of the GaN epitaxial layer are presented and discussed. By adopting an external GaCl3 material supply system, high-speed rotation was applicable, and its effect was confirmed. The results show that when THVPE was used under growth pressure of 600 mbar at 900 °C–950 °C, the surface reaction rate was sufficiently high, and the GaN epitaxial layer was grown under conditions of controlled raw-material supply rates. High growth rates (40–50 μm h−1) and relatively low threading dislocations (∼7 × 107 cm−2) were achieved on 4° off 4H-SiC(000-1)C despite the large lattice mismatch (3.1%) between SiC and GaN and without any buffer layers by introducing step flow growth and growth on a high-quality 4H-SiC substrate. We found that epitaxial layers with a smooth surface morphology can be grown on 4H-SiC(000-1)C compared with growth on 4H-SiC(0001)Si.

Crystallinity control of SiC grown on Si by sputtering method

We investigated a method of controlling the crystallinity of an n-type SiC (n-SiC) layer grown on a p-type 4°-off-axis Si(111) (p-Si) substrate by our sputtering method for use as SiC/Si devices. An n-SiC layer grown on p-Si at 810°C exhibits columnar 3C-SiC(111) crystal growth. However, it contains many defects near the n-SiC/p-Si interface. We then propose a method in which a 10-nm-thick nondoped SiC (i-SiC) interlayer is grown at a low temperature of 640°C prior to the growth of the n-SiC layer at 810°C, which results in a decrease in the number of defects at the SiC/p-Si interface and an intensive increase in the crystallinity of the n-SiC, compared with that of n-SiC grown at 810°C without the interlayer, probably via effective interlayer reconstruction and an enhancement in the crystallinity of the i-SiC interlayer itself during the n-SiC growth. Furthermore, the n-SiC/i-SiC-interlayer/p-Si structure was applied as a Si-based solar cell and the energy conversion efficiency of the n-SiC/p-Si solar cell effectively increased with the insertion of the i-SiC interlayer.

Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates.

A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the “melt-back” effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 μm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude.

Si Surface Preparation for Heteroepitaxial Growth of SiC Using <i>In Situ</i> Oxidation

To achieve high quality SiC growth on Si substrate, it is essential to get a smooth Si surface without forming SiC and graphitic islands during the surface cleaning and before the carbonisation process. In this paper, a novel in-situ surface cleaning method designed for the hetero-epitaxial growth of SiC on Si substrate is developed using a custom-made low-pressure chemical vapour deposition reactor. The results indicate that the combination of ramping in oxygen and subsequent flowing of SiH4 avoids the contamination of Si, enables the oxide layer to be removed smoothly, and subsequently creates a smooth Si surface with regular atomic steps. SiC grown on off-axis Si has better crystallinity and significantly smaller roughness than that grown on on-axis Si.

Misorientation dependent epilayer tilting and stress distribution in heteroepitaxially grown silicon carbide on silicon (111) substrate

The advantages and disadvantages of using off-axis substrates for heteroepitaxial growth of 3C-SiC on Si(111) substrates are investigated in this paper. 3C-SiC is deposited on on-axis and 4° off-axis 150mm Si(111) substrates using low pressure chemical vapour deposition. The dependence of surface morphology, roughness, crystallinity, alignment between the epilayer and the substrate, and film stress are evaluated using atomic force microscopy, X-ray diffraction, and wafer curvature measurement. Highly parallel steps are observed on both on-axis and off-axis Si substrates after surface preparation, yet step density is doubled and step height is much larger (>21 times of single step height) for 4° off-cut Si compared to on-axis Si. X-ray diffraction results indicate that SiC grown on on-axis Si substrates are well-aligned with the Si substrates, while the SiC grown on off-axis substrates are tilted positively by as large angle as 1.66°. The well-aligned SiC grown on on-axis Si substrate exhibits lower and uniform residual stress compared to the film grown on off-axis Si substrates, which exhibits a nonuniform distribution of higher stress. The stress distribution is found to be dependent on Si surface step direction and height. These misorientation dependent tilting and stress distribution mechanisms are expected to be applicable to other hetero-epitaxial growth systems with similar mismatch magnitude.

Epitaxial graphene on single domain 3C-SiC(100) thin films grown on off-axis Si(100)

The current process of growing graphene by thermal decomposition of 3C-SiC(100) on silicon is technologically attractive. Here, we study epitaxial graphene on single domain 3C-SiC films on off-axis Si(100). The structural and electronic properties of such graphene layers are explored by atomic force microscopy, x-ray photoelectron spectroscopy, and Raman spectroscopy. Using low energy electron diffraction, we show that graphene exhibits single planar domains. Near-edge x-ray absorption fine structure is used to characterize the sample, which confirms that the graphene layers present sp2 hybridization and are homogeneously parallel to the substrate surface.

Selective Area Growth of InP on On-Axis Si(001) Substrates with Low Antiphase Boundary Formation

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four side-walls of the Shallow Trench Isolation. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

(Invited) Selective Area Growth of InP on On-Axis Si(001) Substrates with Low Antiphase Boundary Formation

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation mechanism during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four STI side-walls. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

Selective Epitaxial Growth of InP in STI Trenches on Off-Axis Si (001) Substrates

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the thermal budget for surface clean and double step formation. The atomic steps on the Ge surface were recovered after a bake at 680°C. Smooth nucleation layer was obtained at 420°C on the Ge surface. Baking the Ge surface in As ambient facilitates the InP nulceation and improves the InP crystalline quality. This improvement is attributed to the effective As adsorption on the Ge surface and the polar Ge:As surface prevents the islanding of InP seed layer. Stacking faults were found in the InP layers as a result of threading dislocation dissociation and high quality InP layers were obtained in trenches with aspect ratio greater than 2.

Selective Area Growth of InP in Shallow-Trench-Isolated Structures on Off-Axis Si(001) Substrates

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates off-cut toward (111). Extended defect-free InP layers were obtained in the top region of 100 nm wide trenches. A thin Ge epitaxial layer was used as an intermediate buffer layer between the Si substrate and the InP layer. A Ge buffer was used to reduce the thermal budget for surface clean and to promote double-step formation on the surfaces. Baking the Ge surface in an As ambient improved the InP surface morphology and crystalline quality. InP showed highly selective growth in trenches without nucleation on . However, strong loading effects were observed at all growth pressures, which induced variation in local growth rates. We found trench orientation dependence of facet and stacking fault formation. More stacking faults and nanotwins originated from the STI sidewalls in trenches. High quality InP layers were obtained in the top of the trenches along [110]. The stacking faults generated by the dissociation of threading dislocations are trapped at the bottom of the trenches with an aspect ratio greater than 2.

Bow in 6 Inch High-Quality Off-Axis (111) 3C-SiC Films

Growth of 3C-SiC films on an off-axis (111) Si substrate, with a miscut of 4° towards the <110> direction, is here reported. An extensive material characterization has been conducted by means of Scanning Electron Microscopy (SEM), Transmission Electron Microscopy (TEM), X-Ray Diffraction (XRD) and Raman spectroscopy, indicating a very promising film quality with extremely flat surface and interface. Notwithstanding the excellent film quality, the wafer bow is still limiting its full employment in device realization.

High-quality 6 inch (111) 3C-SiC films grown on off-axis (111) Si substrates

Growth of single crystal 3C-SiC films on large area off-axis (111) Si substrate by chemical vapour deposition technique is here reported. The growth was conducted on off-axis Si substrates due to the ability of the misorientation to reduce anti-phase disorder in the 3C-SiC film. 3C-SiC films show an extremely flat surface and interface, stimulating further interest for electrical and mechanical device applications even if a very strong bow, due to the strain induced by the growth process, is observed. Film quality was proved to be high by several investigation techniques and a study of the crystalline defects is also presented. Optical profilometer measurements were also conducted to evaluate accurately the asymmetric curvature of the whole system.

Effect of the miscut direction in (111) 3C-SiC film growth on off-axis (111)Si

Two miscut directions of (111) Si substrate on 3C-SiC heteroepitaxial growth have been studied with the resulting 3C-SiC stress and defects as a function of miscut axis direction toward [110] and [112] of (111) Si analyzed. We studied this dependency from an experimental point of view, investigating the structural properties of 3C-SiC, and using a kinetic Monte Carlo method on superlattice to confirm our experimental findings with numerical simulations. Residual stress and stacking fault density were halved by growing on a (111) Si substrate off-cut toward the [110] direction. A different surface morphology was revealed between the two inclinations.

Towards Large Area (111)3C-SiC Films Grown on Off-Oriented (111)Si

The choice of off-axis (111) Si substrates is poorly reported in literature despite of the ability of such an oriented Si substrate in the reduction of stacking faults generation and propagation. The introduction of off-axis surface would be relevant for the suppression of incoherent boundaries. We grew 3C-SiC films on (111) Si substrates with a miscut angle from 3° to 6° along <110> and <11 >. The film quality was proved to be high by X-Ray diffraction (XRD) characterization. Transmission electron microscopy was performed to give an evaluation of the stacking fault density while pole figures were conducted to detect microtwins. Good quality single crystal 3C-SiC films were finally grown on 6 inch off-axis (111)Si substrate. The generated stress on both 2 and 6 inch 3C-SiC wafers has been analyzed and discussed.

6H and 4H-SiC Avalanche Photodiodes

We report on the fabrication and testing of SiC p-i-n avalanche photodiodes. APDs of 0.25 mm2 area on a-plane (1120) 6H-SiC as well as off-axis Si face 6H and 4H-SiC were successfully fabricated. A beveled mesa was used as edge termination. Recessed windows were formed using reactive ion etching to enhance low-wavelength UV performance. We performed current-voltage tests with and without UV illumination to determine dark current, photocurrent, and gain on selected devices. Dark current was less than 1 pA at 0.5Vbr on multiple devices. Quantum efficiency of 40% or greater was observed for all orientations and polytypes.