nvSRAM Cell Research Articles

Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell

Supply voltage scaling along with the use of non-volatile memory (NVM) device has proven to be the viable approaches for reducing both static and dynamic power consumption in SRAM's. The non-volatile SRAM has power down mode, however at lower supply voltage, the performance of the cell is affected due to process variations. So, to overcome this issue, this paper presents a 13-transistor process invariant nvSRAM cell. The cell introduces Schmitt Trigger invertor nvSRAM cell structure instead of CMOS inverter in existing cells. This modification provide tolerance to process variations by making the proposed cell operate at the lowest minimum power supply voltage at 6σ failure point in comparison to others, by considering both static and dynamic measure. Also, the proposed cell consumed 33.4X lower leakage power than the existing one at their respective Vmin.

Schmitt Trigger 12T1M Non-volatile SRAM cell with improved process variation tolerance

This paper presents a Schmitt Trigger (ST) based 12T1M non-volatile static random-access memory (nvSRAM) cell which significantly provides tolerance against process variations. The memristor M1 is connected between internal node Q and bitline RBL through read pass transistor. The impact of process variation is studied on margin and delay performances of proposed and existing read decoupled (RD) nvSRAM cells. The proposed cell achieves 1.62X, 1.17X and 1.33X higher write, read and hold margins, respectively, in comparison to existing RD nvSRAM cells. Furthermore, the maximum reduction in write, read and hold failure probabilities by 105×, 104× and 104×, respectively, is observed for proposed cell. The overall Vmin of proposed cell is found as 425 mV which is minimum among the existing RD counterparts. In addition, there is significant reduction in leakage power consumption and write/read delay deviation for the proposed cell. The store/restore performance of the proposed cell is same as most of the considered cells. All the comparison are made using 32 nm CMOS PTM model and at Vdd = 0.6 V. The effect of supply voltage variation is also studied on the performance of proposed and existing RD nvSRAM cells for the sake of completeness.

A novel read decoupled 8T1M nvSRAM cell with improved read/write margin

A novel read decoupled 8T1M nvSRAM cell with improved read/write margin

A novel read decoupled 8T1M nvSRAM cell for near threshold operation

The SRAM is mainstay in on-chip memories due to easier integration with standard processing technology and high performance. The SRAM cell is required to have the reliable performance of at strong inversion region as well as near threshold region. The performance of the SRAM cell degrades near threshold voltage due to the increase in the susceptibility to the noise. Also, the idle cells in the SRAM array consume power which is undesirable. A new nvSRAM cell is introduced in this paper which can maintain its performance near threshold voltage. The power consumption is reduced up to 99.7% during write ‘1’ operation. Also, the writability is improved by 69% in comparison to the existing counterparts. The store/restore delay and energy are improved by 70% and 47% respectively. The simulations are carried out using PTM model of 32 nm PTM model of CMOS technology node for different supply voltage. The simulations at different technology node are also carried out to validate the results.

Simulations of single event effects in 6T2C-based ferroelectric non-volatile static random access memory

The single event effects (SEEs) on ferroelectric Hf0.5Zr0.5O2 capacitor-based non-volatile static random access memory (nvSRAM) were investigated by simulation. A nvSRAM cell integrated with two ferroelectric Hf0.5Zr0.5O2 capacitors is proposed in this study. A macro-model of the ferroelectric Hf0.5Zr0.5O2 capacitor, extracted from the real fabricated devices, is utilized for simulation analysis. Fundamental store and recall operations of the proposed nvSRAM design have been demonstrated. An independent double exponential current source was utilized and injected into specific circuit nodes to simulate the heavy ion induced single event transient current. The simulation results show that the transient pulse current is possible to upset the logic state of the memory cell from 1 to 0, but whether it can recover in a short time period after the upset errors depends on the exact value of linear energy transfer for the injected particles. In addition, increasing the remnant polarization (P r) and decreasing the coercive voltage (V c) and film thickness of ferroelectric capacitors can mitigate the influence of SEEs, which provides guidance for process hardening techniques aiming at space applications.

A Low Power 4T2C nvSRAM With Dynamic Current Compensation Operation Scheme

This study proposed a novel nonvolatile static random access memory (nvSRAM) cell with two ferroelectric capacitors (FeCAPs) embedded inside a 4T SRAM cell, i.e., 4T2C, for minimal area penalty and full logic compatibility. The FeCAP with 10-nm-thick Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> film shows excellent ferroelectricity (Pr = 15 μC/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and good memory characteristics (cycles 1011). The 4T2C nvSRAM is capable of storing and restoring previous memory states for nonvolatile data storage. To compensate the leakage current in the dynamic nodes of 4T load less SRAM, we propose a dynamic current compensation operation scheme by exploiting the polarization-dependent leakage current of FeCAP. Outstanding characteristics were achieved in this nvSRAM cell: 1) elimination of the dc path; 2) ultralow store and restore power consumption; and 3) high area efficiency.

A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET

This paper proposes a new 8T nonvolatile SRAM (nvSRAM) cell employing ULP FinFETs and ferroelectric FinFETs to enable energy-efficient and low-latency store/recall operations. Different from other types of nvSRAM requiring additional circuitry or nonvolatile memories connected to a standard 6T SRAM cell to achieve nonvolatility, the proposed hybrid nvSRAM cell reduces the area penalty by embedding the nonvolatile ferroelectric FinFETs in a 6T SRAM cell without sacrificing the cell stability, read/write performance and power consumption.

A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications

Powering billions of devices is one of the most challenging barrier in achieving the future vision of IoT. Most of the sensor nodes for IoT based systems depend on battery as their power source and therefore fail to meet the design goals of lifetime power supply, cost, reliable sensing and transmission. Energy harvesting has the potential to supplant batteries and thus prevents frequent battery replacement. However, energy autonomous systems suffer from sudden power variations due to change in external natural sources and results in loss of data. The memory system is a main component which can improve or decrease performance dramatically. The latest versions of many computing system use chip multiprocessor (CMP) with on-chip cache memory organized as array of SRAM cell. In this paper, we outline the challenges involved with the efficient power supply causing power outage in energy autonomous/self-powered systems. Also, various techniques both at circuit level and system level are discussed which ensures reliable operation of IoT device during power failure. We review the emerging non-volatile memories and explore the possibility of integrating STT-MTJ as prospective candidate for low power solution to energy harvesting based IoT applications. An ultra-low power hybrid NV-SRAM cell is designed by integrating MTJ in the conventional 6T SRAM cell. The proposed LP8T2MTJ NV-SRAM cell is then analyzed using multiple key performance parameters including read/write energies, backup/restore energies, access times and noise margins. The proposed LP8T2MTJ cell is compared to conventional 6T SRAM counterpart indicating similar read and write performance. Also, comparison with the existing MTJ based NV-SRAM cells show 51–78% reduction in backup energy and 42–70% reduction in restore energy.

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

This paper proposes a novel scheme for a low-power non-volatile (NV) memory that exploits a two-level arrangement for attaining single event/multiple bit upsets (SEU/MBU) tolerance. Low-power hardened NVSRAM cell designs are initially utilized at the first level; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. A soft error rate (SER) analysis is also pursued to confirm the findings of the critical charge-based analysis. Simulation of these cells shows that their operation has a very high SEU tolerance, the charges in the nodes of the circuits for non-volatile storage and gate leakage current reduction have very high values, thus ensuring that a SEU will highly unlike affect the correct functions. A novel memory scheme with the proposed NVSRAM cells is proposed for tolerating MBU; in this scheme, only the error detection circuitry is required, because error correction is provided by the non-volatile elements of the NVSRAM cells. Simulation results show that the proposed scheme is very efficient in terms of delay and number of transistors (as measure of complexity). Moreover, the very high critical charge of some of the proposed cell designs reduces the number of MBU appearing as errors at the outputs of the memory, thus further reducing the error detection hardware required by the proposed scheme. An extensive evaluation and comparison of different schemes are presented.

Analysis, measurement, and simulation of dynamic write inhibit in an nvSRAM cell

Dynamic write inhibit (DWI) is a method of selectively inhibiting the programming (writing) of nonvolatile semiconductor memory cells. Its primary use is in silicon nitride oxide semiconductor (SNOS) and metal nitride oxide semiconductor (MNOS) memories, although it may be generalized to other nonvolatile technologies. This technique is based on a mechanism generally known as deep-depletion channel shielding (DDCS). A characterization of this phenomenon from the vantage points of analytic, experimental, and numerical simulations is presented. In addition, a brief review of the literature and the introduction of a novel memory cell used in a 64K nonvolatile static random access memory (nvSRAM) demonstrate the need for this better physical understanding.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>