A Low Power 4T2C nvSRAM With Dynamic Current Compensation Operation Scheme

Abstract

This study proposed a novel nonvolatile static random access memory (nvSRAM) cell with two ferroelectric capacitors (FeCAPs) embedded inside a 4T SRAM cell, i.e., 4T2C, for minimal area penalty and full logic compatibility. The FeCAP with 10-nm-thick Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> film shows excellent ferroelectricity (Pr = 15 μC/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and good memory characteristics (cycles 1011). The 4T2C nvSRAM is capable of storing and restoring previous memory states for nonvolatile data storage. To compensate the leakage current in the dynamic nodes of 4T load less SRAM, we propose a dynamic current compensation operation scheme by exploiting the polarization-dependent leakage current of FeCAP. Outstanding characteristics were achieved in this nvSRAM cell: 1) elimination of the dc path; 2) ultralow store and restore power consumption; and 3) high area efficiency.