NOR Gates Research Articles

Inverter and Universal Gates Implementation Using Novel Core Insulator Double Gate (CIDG) MOSFETs

The Core Insulator Double Gate (CIDG) MOSFET has been explored for digital applications in which the presence of core insulator diminishes the bulk conduction and reduces the off state current. The drain currents of n- and p-type CIDG MOSFETs are matched by tuning gate work functions to deliver the symmetrical pull-up and pull-down characteristics. The inverter and universal logic gates (NAND and NOR) have been designed and implemented to show the usability of the CIDG MOSFETs for digital applications. The DC and transient characteristic of the inverter along with Static Noise Margin (SNM) and time delay parameters have been examined. The designed Inverter shows steeper voltage transfer characteristics, reduced short circuit power dissipation and improved noise immunity. The CIDG MOSFET based NAND and NOR gate implementation and validation by transient analysis have been shown for the first time to the best knowledge of the authors. Also, the rise and fall times of the inverter, NAND and NOR gates have been found to be improved as compared to the DG MOSFET counterparts. The present analysis establishes that CIDG MOSFETs are useful in designing digital circuits with improved performance.

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

Fundamental to digital signal processing applications such as the Arithmetic Logic Unit (ALU), logic gates serve as the foundational components. This paper presents NOR and NAND gates engineered for operation within the ultra-low voltage (LV) and low power domains (LP). Utilizing the floating gate MOSFET (FGMOS) approach, this study adopts a strategy to enhance performance, focusing on reducing design complexity and minimizing power consumption.The proposed FGMOS-NAND/NOR gate design is investigated for important device parameters such as power (pwr), delay (tp), power delay product (PDP), and energy delay product (EDP). At 0.7 V supply, the overall power consumption of the FGMOS NOR and NAND gates is 0.442 nW and 0.323 nW, respectively. Further, carbon nanotube field effect transistor (CNTFET) technology is used to implement NOR and NAND gates in this research work. A rigorous comparative analysis was conducted in this research study to assess the performance of non-conventional technologies, specifically field-effect transistors with floating gate (FGMOS) and carbon nanotube field-effect transistors (CNFET), in comparison to the conventional complementary metal-oxide-semiconductor (CMOS) technology. Notably, our investigation revealed that when carbon nanotube field-effect transistor (CNTFET) technology is synergistically employed in conjunction with FGMOS technology, the overall circuit performance is significantly enhanced. Furthermore, in order to estimate the robustness and reliability of the proposed designs, comprehensive analysis pertaining to delay and power-delay product (PDP) variability were meticulously carried out within the scope of this research article.

Enhancement-Mode Ambipolar Thin-Film Transistors and CMOS Logic Circuits using Bilayer Ga2O3/NiO Semiconductors.

Recent advancements in power electronics have been driven by Ga2O3-based ultrawide bandgap (UWBG) semiconductor devices, enabling efficient high-current switching. However, integrating Ga2O3 power devices with essential silicon CMOS logic circuits for advanced control poses fabrication challenges. Researchers have introduced Ga2O3-based NMOS and pseudo-CMOS circuits for integration, but these circuits may either consume more power or increase the design complexity. Hence, this article proposes Ga2O3-based CMOS realized using heterogeneous 3D-stacked bilayer ambipolar transistors. These ambipolar transistors consist of HfO2/NiO/Ga2O3/NiO/HfO2 heterostructures that are wrapped around by the Ti/Au gate electrode, resulting in record high electron and hole current on/off ratios of 109 and 107. The threshold voltage, subthreshold swing, and current density measured from 100 ambipolar devices (across 5 batches) are around -7.99 ± 0.92 V (p-channel) and 7.81 ± 0.81 V (n-channel), 0.59 ± 0.07 V/dec (p-channel) and 0.61 ± 0.06 V/dec (n-channel), and 0.99 ± 0.26 mA/mm (p-channel) and 58.23 ± 12.99 mA/mm (n-channel), respectively. All the 100 ambipolar devices showed decent long-term stability over a period of 200 days, exhibiting reliable electrical performance. The threshold voltage shift (ΔVTH) after negative bias stressing for a period of 3500 s is around 11.52 V (p-channel) and 10.21 V (n-channel), respectively. Notably, the n-channels exhibit ∼2 orders higher on/off ratio than the best Ga2O3 unipolar transistors at 300 °C. Moreover, the polarities of ambipolar transistors are reconfigurable into p- or n-MOS, which are integrated to demonstrate CMOS inverter, NOR, and NAND logic gates. The switching periods from "0" to "1" and from "1" to "0" of NOR are 0.12 and 0.17 μs, and those of NAND are 0.16 and 0.13 μs. This work lays the foundation of oxide-semiconductor-based CMOS for future integrated electronics.

Compositional Engineering of Cu-Doped SnO Film for Complementary Metal Oxide Semiconductor Technology.

Metal oxide semiconductor (MOS)-based complementary thin-film transistor (TFT) circuits have broad application prospects in large-scale flexible electronics. To simplify circuit design and increase integration density, basic complementary circuits require both p- and n-channel transistors based on an individual semiconductor. However, until now, no MOSs that can simultaneously show p- and n-type conduction behavior have been reported. Herein, we demonstrate for the first time that Cu-doped SnO (Cu:SnO) with HfO2 capping can be employed for high-performance p- and n-channel TFTs. The interstitial Cu+ can induce an n-doping effect while restraining electron-electron scatterings by removing conduction band minimum degeneracy. As a result, the Cu3atom%:SnO TFTs exhibit a record high electron mobility of 43.8 cm2 V-1 s-1. Meanwhile, the p-channel devices show an ultrahigh hole mobility of 2.4 cm2 V-1 s-1. Flexible complementary logics are then established, including an inverter, NAND gates, and NOR gates. Impressively, the inverter exhibits an ultrahigh gain of 302.4 and excellent operational stability and bending reliability.

Reconfigurable Skyrmion-Based Logic Gates: Versatile Design and Full-Scale Implementation.

Herein, we investigate the behavior of skyrmions within a racetrack design incorporating voltage-controlled magnetic anisotropy (VCMA) gates. Our analysis encompassed multiple forces, including spin currents and anisotropy gradients induced by bias voltages. As a result, the efficient control of skyrmion dynamics was achieved across various VCMA gate configurations. Building upon these findings, we propose an efficient approach to reconfigurable skyrmion logic (RSL) in a thin antiferromagnetic (AFM) film through a versatile design. Our RSL harnesses the selective integration of VCMA, spin-polarized currents, and skyrmion-skyrmion (sky-sky) interactions to implement multiple logic gates, including AND, OR, XOR, NOT, NAND, XNOR, and NOR. The design brings a significant advantage with its simplified fabrication process, making the implementation of the RSL practical and accessible for various applications. Furthermore, the RSL enables seamless dynamic switching between logic gates, thereby enhancing its multifunctionality. Additionally, the strategic incorporation of sky-sky interactions and skyrmion-edge repulsion prominently facilitates the realization of complex gates, such as NAND, XNOR, and NOR gates, that typically require intricate design efforts. Hence, this streamlined integration of RSL, coupled with its adaptability to changing computational needs, underscores its potential as a practical solution for implementing high-functionality skyrmion-based logic gates.

Flexible nanomechanical bit based on few-layer graphene.

Mechanical computers have gained intense research interest at size scales ranging from nano to macro as they may complement electronic computers operating in extreme environments. While nanoscale mechanical computers may be easier to integrate with traditional electronic components, most current nanomechanical computers are based on volatile resonator systems that require continuous energy input. In this study, we propose a non-volatile nanomechanical bit based on the quasi-stable configurations of few-layer graphene with void defects, and demonstrate its multiple quasi-stable states by deriving an analytic relationship for the void configuration based on a competition between the bending energy and the cohesive energy. Using this nanomechanical bit, typical logic gates are constructed to perform Boolean calculations, including NOT, AND, OR, NAND and NOR gates, and demonstrate reprogrammability between these logic gates. We also study the accuracy and the stability of the nanomechanical bits based on the few-layer graphene. These findings provide a novel approach to realize the nanomechanical computing process.

Surface engineering of high-k polymeric dielectric layers with a fluorinated organic crosslinker for use in flexible-platform electronics.

High-k polymeric layers were prepared by combining various functional groups and were applied as gate dielectrics for practical organic field-effect transistors (OFETs). Crosslinking of the polymeric layers through UV-assisted organic azide fluorine-based crosslinkers induced dramatic improvements in the electrical performance of the OFET, such as field-effect mobility and bias-stress stability. Our synthesis and manufacturing method can be a useful technique for ensuring device operation stability and electrical property enhancement. With this analysis, we further applied our polymer-dielectric OFETs to flexible-platform-based electronic components, including unit OFETs and simple logic devices (NOT, NAND, and NOR gates). The outcomes of this research and development suggest a suitable method for the low-cost mass production of large-area flexible and printable devices, using a printing-based approach to replace current processes.

Simulation of all‐optical NOR gate design with improved extinction ratio using semiconductor optical amplifier

AbstractOptical computers, leveraging the advantages of light characteristics, hold the potential to outperform electronic computers significantly. The role of all‐optical logic gates is pivotal in realizing such high‐performance computing systems. This research introduces a streamlined design for an all‐optical NOR logic gate utilizing a semiconductor optical amplifier. The proposed gate operates at a remarkable data rate of 40 Gbps, achieving an excellent extinction ratio of 20.285 dB. Notably, the design exhibits very low dispersion (−0.029 × 10+006 ps/nm) and an impressively low bit error rate of 4.27 × 10−26.

Ultra compact, high contrast ratio all optical NOR gate using two dimensional photonic crystals

An all-optical NOR gate is implemented using a two-dimensional photonic crystal waveguide. The paper provides a structure of an all-optical NOR gate constructed by introducing a line and point defect. The proposed NOR gate uses a hexagonal lattice structure with E shaped waveguide. The contrast ratio, response time and bit rate of three input NOR gate are 29.59 dB, 0.8 ps and 1.19 Tbps, respectively. The proposed gate is constructed with the operating wavelength of 1550 nm. The structure has been simulated and analyzed using Finite Difference Time Domain (FDTD) and Plane Wave Expansion (PWE) methods. It offers high contrast ratio, better response time with ultra-compact size. Hence it is suitable for high speed optical integrated circuits and switching devices.

Simulation Modelling of Silicon Gated Field Emitter Based Electronic Circuits

Vacuum transistors (VTs) are promising candidates in electronics due to their fast response and ability to function in harsh environments. In this study, several oscillator and logic gate circuit simulations using VTs are demonstrated. Silicon-gated field emitter arrays (Si-GFEAs) with 1000 × 1000 arrays were used experimentally to create a VT model. First, transfer and output characteristics sweeps were measured, and based on those data, an LTspice vacuum transistor (VT) model was developed. Then, the model was used to develop Wein and Ring oscillator circuits. The circuits were analytically simulated using LTspice, where the collector bias voltage was 200 V DC, and the gate bias voltage was 30–40 V DC. The Wein oscillator circuit produced a frequency of 102 kHz with a magnitude of 26 Vpp. The Ring oscillator produced a frequency of 1.14 MHz with a magnitude of 4 Vpp. Furthermore, two logic circuits, NOR and NAND gates, were also demonstrated using LTspice modeling. These simulation results illustrate the feasibility of integrating VTs into functional integrated circuits and provide a design approach for future on-chip vacuum transistors applied in logic or radio-frequency (RF) devices.

Large-scale and stacked transfer of bilayers MoS2 devices on a flexible polyimide substrate

Two-dimensional transition metal dichalcogenides (TMDs), as flexible and stretchable materials, have attracted considerable attention in the field of novel flexible electronics due to their excellent mechanical, optical, and electronic properties. Among the various TMD materials, atomically thin MoS2 has become the most widely used material due to its advantageous properties, such as its adjustable bandgap, excellent performance, and ease of preparation. In this work, we demonstrated the practicality of a stacked wafer-scale two-layer MoS2 film obtained by transferring multiple single-layer films grown using chemical vapor deposition. The MoS2 field-effect transistor cell had a top-gated device structure with a (PI) film as the substrate, which exhibited a high on/off ratio (108), large average mobility (∼8.56 cm2 V−1 s−1), and exceptional uniformity. Furthermore, a range of flexible integrated logic devices, including inverters, NOR gates, and NAND gates, were successfully implemented via traditional lithography. These results highlight the immense potential of TMD materials, particularly MoS2, in enabling advanced flexible electronic and optoelectronic devices, which pave the way for transformative applications in future-generation electronics.

Ultrafast nonlinear absorption in MoTe2 and MoTe2/MoS2 nanocomposite films and its application to all-optical logic gates

We present a detailed theoretical analysis of ultrafast saturable absorption (SA) and reverse SA (RSA) in MoTe2 nano-films with femtosecond (fs) laser pulses at 800 nm. A transition from RSA to SA occurs on increasing the thickness from 30 nm to 80 nm at a constant pump intensity of 141 GW cm−2. On the other hand, a transition from SA to RSA occurs upon increasing the pump intensity in an 80 nm thick MoTe2 nano-film. Theoretical results are in good agreement with reported experimental results. The effect of pump pulse intensity, pulse width, nonlinear absorption coefficient and sample thickness has been studied to optimize the SA ↔ RSA transition. The results for low-power and high contrast all-optical switching in MoTe2 nano-films have been used to design all-optical fs NOT, OR, AND, as well as the universal all-optical NOR and NAND logic gates. The SA behavior of MoTe2/MoS2 nanocomposite films has been used to design all-optical AND and OR logic gates. The nanocomposite films of MoTe2/MoS2 possess a larger nonlinear optical response in comparison to MoTe2 and MoS2 nano-films and, therefore, all-optical logic gates designed using nanocomposite films result in a good switching contrast compared to pure MoTe2 nano-films. Ultrafast operation at relatively low pump intensities demonstrates the applicability of MoTe2 and MoTe2/MoS2 nano-films for ultrafast all-optical information processing.

Integrated Logic Circuits Based on Wafer-Scale 2D-MoS2 FETs Using Buried-Gate Structures.

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) materials, such as molybdenum disulfide (MoS2), stand out due to their atomically thin layered structure and exceptional electrical properties. Consequently, they could potentially become one of the main materials for future integrated high-performance logic circuits. However, the local back-gate-based MoS2 transistors on a silicon substrate can lead to the degradation of electrical characteristics. This degradation is caused by the abnormal effect of gate sidewalls, leading to non-uniform field controllability. Therefore, the buried-gate-based MoS2 transistors where the gate electrodes are embedded into the silicon substrate are fabricated. The several device parameters such as field-effect mobility, on/off current ratio, and breakdown voltage of gate dielectric are dramatically enhanced by field-effect mobility (from 0.166 to 1.08 cm2/V·s), on/off current ratio (from 4.90 × 105 to 1.52 × 107), and breakdown voltage (from 15.73 to 27.48 V) compared with a local back-gate-based MoS2 transistor, respectively. Integrated logic circuits, including inverters, NAND, NOR, AND, and OR gates, were successfully fabricated by 2-inch wafer-scale through the integration of a buried-gate MoS2 transistor array.

Ultra-broadband and ultra-compact chip-integrated logic gates based on an inverse design method

The Si-based chip-integrated OR, XOR, NOR, AND and NAND all-optical logic gates (AO-LGs) with footprints of 2 μm × 2 μm are inversely designed based on an intelligent method, which combines the method of moving asymptotes (MMA) with the finite element method (FEM). In this method, the substrate is divided into many small units, and the refractive index of each unit will be perturbed according to design expectation. Therefore, the optimized refractive index will be gradient, which divorces from fabrication. Binary reconstruction is the process of changing the gradient media into binary media, by filtering out the gradient virtual media, smoothing the boundaries, and refilling Si or air on the substrate to form a new structure. Numerical simulations demonstrate that all the AO-LGs designed by this method work effectively. The contrast ratio (CR) of OR/XOR gate ranges from 23.50 dB to 25.50 dB, NOR gate ranges from 6.33 dB to 7.91 dB, AND gate ranges from 4.44 dB to 6.13 dB, and NAND gate ranges from 8.85 dB to 10.07 dB. And these designed AO-LGs achieve nearly ten times more broad bandwidth than the other reported conventional gates without suffering other performances too much. The OR/XOR, and NOR gate functions well in a broad band range from 800 nm to 1600 nm, and from 850 nm to 1350 nm. AND gate functions well from 1000 nm to 1240 nm and from 1310 nm to 1400 nm. NAND gate functions well from 1360 nm to 1530 nm. It is expected that such a robust method can serve extensive applications in designing photonic devices, and the compact logic gates may contribute to broad applications of future optical computing and signal processing.

Design and analysis of SOA-MZI based optical digital circuits for high speed optical networks

This paper explores using Semiconductor Optical Amplifier assisted Mach-Zehnder Interferometer (SOA-MZI) configuration for designing various all-optical digital circuits. A specific focus on the design and analysis of all-optical inverters, decimal-to-binary code converters, and hexa decimal-to-binary code converters operating at a speed of 10 Gbps is given. These circuits employ OR, XOR, and NOR gates. The SOA-MZI configuration capitalizes on the nonlinear properties of the SOA to achieve all-optical logic functions. Phase modulation can be transformed into intensity modulation by incorporating the SOA within an interferometer setup and using 3-dB couplers. The Cross-Phase Modulation (XPM) technique, which offers superior performance compared to other types of SOA non-linearity, is employed to make the incoming signal insensitive to polarization. The system was analyzed using an optisystem. The performance achieved was 0.0109 in terms of Eye height, 3.45 e−70 in terms of Bit Error Rate (BER), and 17.66 in terms of Q-factor.

Matched printed carbon nanotube complementary metal-oxide-semiconductor (CMOS) devices for flexible circuits

The development of matched carbon nanotube (CNT) complementary metal-oxide-semiconductor (CMOS) devices still remains a challenge for flexible and low-power-dissipation circuits. In this study, we found a reliable technique to achieve matched CNT CMOS thin-film transistors (TFTs) for integrated circuits (IC) with low power consumption. The enhancement-mode p-type CNT TFTs were obtained using the low-work-function Al gate electrodes and ultrathin (10 nm) Al2O3 dielectrics, which exhibit the average field-effect mobility(μ) of 6.5 cm2V−1s−1, subthreshold swing (SS) down to 70–85 mV/dec and on/off ratio up to 106 at the low working voltages between −1.5 V and 0.5 V, as well the outstanding stability and mechanical flexibility after 10,000 cycles of bending. Then, by adjusting the aspect ratios of the TFT channels and selectively dropping the electron-doping inks into p-type CNT TFTs’ channels, matched n-type and p-type CNT TFTs were obtained. Finally, flexible printed CMOS inverters with high noise tolerance (84% of 1/2 VDD), high voltage gain (over 32), and low power consumption (down to 32.9 pW) were successfully constructed, owing to the work style of CMOS circuits and electrically symmetrical n-type and p-type TFTs. Furthermore, good-performance NAND and NOR gates have been demonstrated. This work can effectively resolve the leakage current issue of flexible carbon-based electronics with the ultra-thin dielectrics by optimizing the conductive ink formula and printing technology.

Design and Validation of a V-Gate n-MOSFET-Based RH CMOS Logic Circuit with Tolerance to the TID Effect

This study designed a radiation-hardened (RH) complementary metal oxide semiconductor (CMOS) logic circuit based on an RH variable-gate (V-gate) n-MOSFET that was resistant to the total ionizing dose (TID) effect and evaluated its tolerance to radiation. Among the different CMOS logic circuits, NOT, NAND, and NOR gates were designed using V-gate n-MOSFETs by employing layout transformation techniques and standard p-MOSFETs. Before the process design, we predicted the radiation damage using modeling and simulation techniques and validated the tolerance by conducting actual radiation tests after the process design. Furthermore, we implemented the CMOS logic circuit process design in a 0.18 µm CMOS bulk process. The actual radiation test applied a total cumulative radiation dose of 25 kGy at 5 kGy per hour in a high-level gamma-ray irradiation facility. Consequently, the resistance of the RH CMOS logic circuit based on the RH V-gate n-MOSFET to the TID effect was validated through experiments.

High‐Speed Operation of Electrochemical Logic Circuits Depending on 3D Construction of Transistor Architectures

AbstractThe emergence of organic electrochemical transistors (OECTs) has opened a new era of printable electronics and bioelectronics, due to their unique advantages including innately superior transconductance and biocompatibility. Despite the foreseeable advancements available from their further implementations in fundamental logic circuitry, however, insufficient operation speeds and short compatibilities to scaling‐down have so far hindered advanced integrations other than biosensing and biosignal amplifications. Here, a 3D‐construction‐dependent operational analysis of OECTs is reported, with which an all‐vertical architectural design enabled unprecedentedly high operating speed and a facile expansion to large‐area and high‐density 3D crossbar arrays. A simple vertical channel architecture completed with solid‐state Ag/AgCl top‐gate electrodes enables an ultrafast redistribution of ions within channels, yielding a state‐of‐the‐art operation frequency reaching 12 MHz V−1. Various printed logic circuit arrays, including NOT, NAND, and NOR gates, with high stability and reproducibility.

A Constitutionally Dynamic Cage Acts as a Convertible and Adaptable Information Manager in Supramolecular Logic

AbstractA three‐component molecular ensemble consisting of the constitutionally dynamic cage 1, rotaxane 2 and luminophore 3 acts as a signal transducer which assimilates three input signals, i. e., Zn2+, H+, and Cu+, to perform individual logic operations (e. g. a 3‐input NOR gate with catalytic output, 3‐input AND gate with optical output) and operates as an unconventional 3‐input demultiplexer.

Memristor-Based D-Flip-Flop Design and Application in Built-In Self-Test

There are several significant advantages of memristors, such as their nano scale, fast switching speed, power efficiency and compatibility with CMOS technology, as one of the alternatives in the next generation of semiconductor storage devices. D-flip-flops (DFFs) based on the traditional CMOS process have some shortcomings, including a large area, high power, and charge leakage when scaling down. However, memristors offer a new approach to the design of DFFs with improved performance. Two simplified edge-triggered DFFs are proposed to reduce the number of devices via the Memristor-Rationed Logic (MRL) method, which utilizes the characteristic of transmitting signals in the two-stage inversion structure. In addition, two new 4-bit Linear Feedback Shift Registers (LFSRs) are designed and verified using the proposed DFFs. Compared to the partially existing LFSRs, the designed LFSRs reduce the number of devices significantly, decrease the power consumption by 32.7% and 33.3% and shorten the delay time by 34.5% and 30.7% for the NOR and NAND gates, respectively. Finally, the proposed falling-edge-triggered DFF is used to implement the major blocks of the Built-In Self-Test(BIST) circuit, and the simulation results confirm their correctness and feasibility.