Nonvolatile SRAM Research Articles

A novel MTCMOS based 8T2M NVSRAM design for low power applications with high temperature endurance

This research investigates, for the first time, a novel eight-transistor-two-memristor (8T2M) nonvolatile static random access memory (NVSRAM) with 7-nm technology. The key innovation in this design lies in the incorporation of multiple-threshold complementary metal oxide semiconductor (MTCMOS) technology with power gating technique, which enables efficient power management and enhanced performance with low leakage current. The implementation of multiple threshold voltage levels allows for dynamic control of transistor behavior, optimizing power consumption and read/write speeds. As compared to a traditional six-transistor (6T) static random access memory (SRAM) cell, it has been ascertained that there is a 33% enhancement in the read margin and an 18% improvement in the write margin. Moreover, the delay for read, write ‘0’ and write ‘1’ is also minimized by 63.89%, 37.99% and 42.77%. Furthermore, the power attenuation is also reduced for read and write by 63.02% and 81.6%, respectively with respect to a conventional SRAM.

An 8T PA Attack Resilient NVSRAM for In-Memory-Computing Applications

The proposed 8T Non-Volatile SRAM (NVSRAM) is designed to be resistant to power analysis (PA) attacks and is suitable for in-memory computing (IMC) applications. Our design uses a two-phase write operation instead of the traditional single-phase write operation, which reduces the correlation between stored data and power consumption during writing and provides resilience against PA attacks. It provides a mean energy difference (MED) of 5aJ, which is 1000 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> less compared to available 6T SRAM cells. The proposed cell also utilizes a common Spin transfer torque (STT) current for both magnetic tunnel junctions (MTJs), which results in more energy efficient and faster store operations. The store operation becomes 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> more energy efficient and 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> faster compared to the available state of the art NVSRAM Cells. The Symmetrical structure of proposed cell and two stage store/restore operation provide PA attack resiliency during store and restore mode of NVSRAM. Additionally, the proposed cell performs IMC for XNOR computation by collocating the weights and activations stored in the same bit cell.

CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration

SRAM-based computing-in-memory (CIM) has been widely explored to accelerate neural networks (NNs). However, it is challenging to store all weights of many modern NNs due to limited on-chip SRAM capacity. This bottleneck induces a large amount of off-chip DRAM accesses and impedes the improvement of performance and energy efficiency. This paper proposes a new approach of computing in resistive random-access memory (ReRAM)-assisted energy-and area-efficient SRAM (CREAM) for accelerating large-scale NNs while eliminating the DRAM access. The NN weights are all stored in high-density on-chip ReRAMs and restored to the proposed non-volatile SRAM (nvSRAM) CIM cells with array-level parallelism. Furthermore, to deal with the influence of ReRAM and CMOS variations, a novel layer-wise and bit-wise weight-configuration search algorithm is proposed by leveraging different sensitivity of each layer in NN models. A data-aware weight-mapping method is also presented to efficiently map NN models to ReRAMs in CREAM for high computation parallelism. The experiment results show 10.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> weight storage density over the standard 6T SRAM array. Evaluations of ResNet-18 and VGG-9 on CIFAR-10/CIFAR-100 datasets show up to 3.47 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> and 1.70 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> energy efficiency over two baseline designs of SRAM-CIM and ReRAM-CIM, respectively, in addition to 15.6% higher accuracy than ReRAM-CIM under device variations.

High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications

Static random access memory (SRAM) plays a key role in the overall performance of electronic systems because of its rapid data processing and transmission speed; however, when the system power supply is cut off, the data stored in the nodes are lost. Thus, this article proposes four nonvolatile SRAM (NVSRAM) cells that use unilateral or bilateral structures with dual complementary series resistive random access memory (RRAM) devices. It is found that the read, write, and hold static noise margins (HSNMs) are comparable with those of the standard 6T-SRAM. Moreover, the store and restore operations operate in parallel at high speed. The store operation delay is only 6 ns for unilateral structures and 5 ns for bilateral structures, and the restore delay is only 10 ns for unilateral structures and 6 ns for bilateral structures. The maximum power consumption among the four structures for storing and restoring a “1” are 1.545 pJ/bit and 134.5 fJ/bit, respectively. Furthermore, the dual complementary series resistor structures can achieve a high restore yield at a resistance ratio of 1.5. Therefore, a high restore yield can be achieved even with large resistance fluctuations caused by the voltage, time, and process.

Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell

Supply voltage scaling along with the use of non-volatile memory (NVM) device has proven to be the viable approaches for reducing both static and dynamic power consumption in SRAM's. The non-volatile SRAM has power down mode, however at lower supply voltage, the performance of the cell is affected due to process variations. So, to overcome this issue, this paper presents a 13-transistor process invariant nvSRAM cell. The cell introduces Schmitt Trigger invertor nvSRAM cell structure instead of CMOS inverter in existing cells. This modification provide tolerance to process variations by making the proposed cell operate at the lowest minimum power supply voltage at 6σ failure point in comparison to others, by considering both static and dynamic measure. Also, the proposed cell consumed 33.4X lower leakage power than the existing one at their respective Vmin.

A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node

Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. The nvSRAM memory cell is realized with UMC CMOS 28 nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. The data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm2.

Schmitt Trigger 12T1M Non-volatile SRAM cell with improved process variation tolerance

This paper presents a Schmitt Trigger (ST) based 12T1M non-volatile static random-access memory (nvSRAM) cell which significantly provides tolerance against process variations. The memristor M1 is connected between internal node Q and bitline RBL through read pass transistor. The impact of process variation is studied on margin and delay performances of proposed and existing read decoupled (RD) nvSRAM cells. The proposed cell achieves 1.62X, 1.17X and 1.33X higher write, read and hold margins, respectively, in comparison to existing RD nvSRAM cells. Furthermore, the maximum reduction in write, read and hold failure probabilities by 105×, 104× and 104×, respectively, is observed for proposed cell. The overall Vmin of proposed cell is found as 425 mV which is minimum among the existing RD counterparts. In addition, there is significant reduction in leakage power consumption and write/read delay deviation for the proposed cell. The store/restore performance of the proposed cell is same as most of the considered cells. All the comparison are made using 32 nm CMOS PTM model and at Vdd = 0.6 V. The effect of supply voltage variation is also studied on the performance of proposed and existing RD nvSRAM cells for the sake of completeness.

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

Design of auto-store circuit for nvSRAM with SONOS access transistor

In this paper, an auto-store circuit that can perform a store and restore operation of non-volatile SRAM (nvSRAM) with access transistor whose gate stack is Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) is designed. The suggested auto-store circuit is consisted by two small circuit parts of a store and restore circuit. The store circuit moves data in SRAM cell into SONOS device before power turns off while a restore circuit recalls the data to SRAM cell when the power is resupplied. When the nvSRAM replaces its conventional access transistor with the SONOS flash memory device, higher word line voltage is needed for a store operation. It demands much energy and additional voltage source to store a data. To overcome this disadvantage, the capacitor component is added in the store and restore circuit which is charged during the normal operation mode. At the moment of the power-off, the store circuit discharges the capacitors and applies higher voltage to the word line for the store operation. When the power is supplied again, the restore circuit discharges the capacitor and applies pre-charge voltage and restore the data to the bit line and word line. The simulation results show that the suggested auto store circuit can perform the store, restore operation in the sudden power off without an additional voltage source.

An 8kb RRAM-Based Nonvolatile SRAM with Pre-Decoding and Fast Storage/Restoration Time

Combining the advantages of low-power consumption of static random access memory (SRAM) with high stability and nonvolatile of resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell was proposed in this paper. In order to solve the problem that data cannot be stored when SRAM is powered off, RRAM technology was introduced into SRAM to realize an SRAM with nonvolatile function. The differential mode was adopted to improve the data restoration speed. Meanwhile, a pre-decoding technology was proposed to realize fast address decoding, and a voltage-mode sensitive amplifier was used to achieve fast amplification of two bit lines, so as to improve the reading speed of the memory. An 8kb nvSRAM was implemented with a CMOS 28 nm 1P9M process. The simulation results show that when the power supply voltage was 0.9 V, the static/read/write noise margin was 0.35 V, 0.16 V and 0.41 V, respectively. The data storage time was 0.21 ns, and restoration time was 0.18 ns. The time for the whole system to read 1 bit of data was 5.2 ns.

Enabling In-Memory Computations in Non-Volatile SRAM Designs

The rapid growth in development of neural networks has necessitated the requirement of large capacity on-chip SRAM’s for Machine Learning accelerators. This has resulted in SRAM’s occupying significant portion of the die area. Furthermore, due to increased short channel effects in advanced CMOS technology nodes, the Vt of the transistors are increased to reduce the leakage power effectively. Vt increase results in direct increase in V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> (minimum operating voltage) of the device. The conventional 6T SRAM with the use of RRAM(R) to store the bitcell storage node values and PTM(S) as a selector device (6T-2R-2S) can help in decoupling V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> and Vt requirement with minimum area overhead. Functionalities of 6T-2R-2S bitcell are investigated to present a 2T-2R-2S mode and SRAM-RRAM hybrid mode of operation, further utilized in performing Compute in Memory(CIM). The above functionalities can be presented in a 8T2R bitcell, that makes use of transistor in place of PTM. 2T-2R-2S/2T-2R mode is a fully non-differential mode of operation, leveraging only the NVM portion of the bitcell. Furthermore, SRAM-RRAM hybrid mode is proposed making use of the SRAM read port transistors to perform read operation of the data stored on the RRAM, during standby mode. The architecture study of set-associative cache made of 6T-2R-2S array is also presented. The 2T-2R-2S/2T-2R mode coupled with SRAM-only mode can be efficiently used to perform CIM for dot product and XNOR computation with co-locating the weights and activations stored onto the same bitcell. System level study highlighting energy efficiency and speedup along with the proposed CIM architecture’s analysis on CIFAR-10 dataset is presented. Design sensitivity analysis with respect to PTM and RRAM parameters is discussed for both the bitcells.

A Symmetric Novel 8T3R Non-Volatile SRAM Cell for Embedded Applications

This paper proposes a symmetric eight transistor-three-memristor (8T3R) non-volatile static random-access memory (NVSRAM) cell. Non-volatile operation is achieved through the use of a memristor element, which stores data in the form of its resistive state and is referred to as RRAM. This cell is able to store the information after power-off mode and provides fast power-on/power-off speeds. The proposed symmetric 8T3R NVSRAM cell performs better instant-on operation compared to existing NVSRAMs at different technology nodes. The simulation results show that resistance of RAM-based 8T3R SRAM cell consumes less power in standby mode and has excellent switching performance during power on/off speed. It also has better read and write stability and significantly improves noise tolerance than the conventional asymmetrical 6T SRAM and other NVSRAM cells. The power dissipation is evaluated at different technology nodes. Hence, our proposed symmetric 8T3R NVSRAM cell is suitable to use at low power and embedded applications.

A Novel STT–SOT MTJ-Based Nonvolatile SRAM for Power Gating Applications

This article proposes novel nonvolatile (NV) static random access memory (SRAM) circuits based on spin transfer torque (STT) and spin orbit torque (SOT) operated magnetic tunnel junction (MTJ) device for energy-efficient power gating circuits. In which, two different designs of 9T-2MTJs and 10T-2MTJ-based NV SRAM circuits are proposed for low power, high noise margin, and faster switching speed with less area overhead. The proposed architecture uses a smaller number of transistor combinations to accommodate low-power operation with compact cell size when compared with available pieces of literature. Also, the combination of nMOS and pMOS transistors in the proposed architecture enhances the driving capability of the circuit for both low and high input operations. Here, the electrical characteristics of the proposed designs have been compared and contrasted with the available 11T-2MTJ and 7T-2D-2MTJ non volatile static random access memory (NVSRAM) and 6T SRAM circuits using a UMC-40 nm design kit and physics-based STT–SOT MTJ Verilog-A Model. The proposed 9T-2MTJ-based NVSRAM was found to be a better alternative and offers improved performance in terms of higher restore noise margin and lower power consumption than other circuits reported at this node. Moreover, the studied 10T-2MTJ exhibits an improved write and hold noise margin than the proposed/available 9T/7T-2D/11T-2MTJ circuits.

Node Voltage and KCL Model-Based Low Leakage Volatile and Non-Volatile 7T SRAM Cells

The current generation aims for Low power electronic gadgets like cell phones, PDAs, etc. This urged demand is met through adopting low power reduction techniques. These gadgets also demand the presence of cache memories, which are fabricated via Static Random Access Memory (SRAM) Cells. Now the challenge is in designing low leakage SRAM cells by adopting power reduction techniques. The proposed work of 7T based Volatile and Non-Volatile SRAM cell is carried through adopting efficient low power reduction technique referred to as Improved Self Controllable Voltage Level (I-SVL). Proposed 7T SRAM cell is based on Improved Self Controllable Voltage Level (I-SVL) technique which controls the supply voltage in Idle and Non Idle mode of SRAM cell. Also Upper-ISVL and Lower-ISVL supplies the Vdd and Vss as per the requirement there by controlling the leakage power. The proposed I-SVL based 7T Volatile and Non-Volatile is designed and simulated using Cadence Virtuoso spectre tool by using CMOS technology with gpdk 45nm. Proposed work carried is efficient in terms of sub threshold and total leakage currents in comparison with the earlier work. The obtained sub threshold and total leakage current of the proposed volatile 7T SRAM cell based on the I-SVL shows improvements in lower values with existing work by 15% and 32%. Also proposed Non-volatile based I-SVL 7T SRAM cell resulted in lesser sub threshold and total leakage current by an amount of 97% and 93% in comparison with the earlier work. The gate leakage current of proposed Non-volatile 7T SRAM cell resulted in 57% lower value in comparison with the earlier work.

A Nonvolatile 7T2M SRAM Cell with Improved Noise Margin for Energy Efficient In Memory Boolean Computations

The current computing systems are facing von Neumann bottleneck (VNB) in modern times due to the high prominence on big-data applications such as artificial intelligence and neuromorphic computing. In-memory computation is one of the emerging computing paradigms to mitigate this VNB. In this paper, a memristor-based robust 7T2M Nonvolatile-SRAM (NvSRAM) is proposed for energy-efficient In-memory computation. The 7T2M NvSRAM is designed using CMOS and memristor with a higher resistance ratio, which improved the write margin by 74.44% and the energy consumption for read and write operation by 5.10% and 9.66% over conventional 6T SRAM at the cost of increment in write delay. The read decoupled path with the VGND line enhances the read margin and read path Ion/Ioff ratio of 7T2M NvSRAM cell by 2.69× and 102.42%, respectively over conventional 6T SRAM. The proposed cell uses a stacking transistor to reduce the leakage power in standby mode by 64.20% over conventional 6T SRAM. In addition to the normal SRAM function, the proposed 7T2M NvSRAM performs In-Memory Boolean Computation (IMBC) operations such as NAND, AND, NOR, OR, and XOR in a single cycle without compute-disturb (stored data flips during IMC). It achieves 4.29-fJ/bit average energy consumption at 1.8 V for IMBC operations

A novel design of high performance and robust ultra-low power SRAM cell based on memcapacitor

The present paper proposes a six-FinFET two-memcapacitor (6T2MC) non-volatile static random-access memory (NVSRAM). In this design, the two memcapacitors are used as non-volatile memory elements. The proposed cell is flexible against data loss when turned off and offers significant improvement in read and write operations compared to previous NVSRAMs. The performance of the new NVSRAM design is evaluated in terms of read and write operation at particular nanometric feature sizes. Moreover, the proposed 6T2MC cell is compared with 8T2R, 8T1R, 7T1R, and 7T2R cells. The results show that 6T2MC has a 5.50% lower write delay and 98.35% lower read delay compared to 7T2R and 7T1R cells, respectively. The 6T2MC cell exhibits 38.86% lower power consumption and 23.80% lower leakage power than 7T2R and 7T1R cells. The proposed cell is significantly improved in terms of HSNM, RSNM, and WSNM compared to 8T2R, 8T1R, 7T2R, and 7T1R cells, respectively. Important cell parameters, such as power consumption, data read/write delay, and SNM, are significantly improved. The superior characteristics of FinFET over MOSFET and the combination of this technology with memcapacitors lead to significant improvement in the proposed design.

Low Power Non-Volatile 7T1M Subthreshold SRAM Cell

A new modified 7T1M non-volatile SRAM cell is presented in this paper for low power applications at subthresholdvoltage (very low voltage) simply by connecting the memristor directly with storage node which is acting as storage elementand adding a transistor in between the two storage nodes with feedback connection gives better performance in terms ofaverage delay, read /write operations and RSNM/WSNM. The memristor based circuits are simulated at subthreshold is anew insight and a new effort in technology made with improvement of approximately 61% and 23% of RSNM and WSNMrespectively compared to existing memory cell 7T1M and power dissipation is decreased by 66% whereas read delay andwrite delay obtained is nominal. Moreover, It has also simulated an adjusting 6T2M and conventional 6T at subthresholdvoltage i.e. VDD=0.3V to compare its stability behaviour at lower supply voltage.

Performances and Stability Analysis of a Novel 8T1R Non-Volatile SRAM (NVSRAM) versus Variability

Static Random-Access Memories (SRAMs) are an integral part of the chip industry, occupying a noticeable share of the memory market due to their high performance and compatibility with CMOS technology. Traditional SRAMs do not have the capacity to retain data after power-off, preventing their use in non-volatile applications. This paper presents a novel Non-Volatile SRAM (NVSRAM) device based on Resistive RAM (RRAM) technology. A comparison between SRAM and the proposed NVSRAM performances is proposed at both cell and memory array level. The comparison covers several metrics such as energy consumption, area and static noise margin (SNM). Moreover, this work proposes a deep analysis of the impact of RRAM variability as well as the CMOS subsystem variability on the NVSRAM performances. The proposed structure demonstrates robust NVSRAM performances in terms of stability and reliability despite RRAM variability.

Resilient Password Manager Using Physical Unclonable Functions

The offline dictionary attacks on the database of passwords (PW) or even hashed PW are damaging as a single server break-in leads to many compromised PWs. In this regard, using Physical Unclonable Functions (PUFs) to increase the security of PW manager systems has been recently proposed. Using PUFs allows replacing the hashed PW with PUF responses, which provide an additional hardware layer of security. In this way, even with accessing the database, an adversary should have physical control of the PUF to find the PWs. However, such a scheme cannot operate without a backup in case of catastrophic failure of the PUFs. The likelihood of a failure is low unless the opponent finds a way to destroy the PUF. The scheme used in this article includes a mechanism to make the system works consistently if the PUF fails, with redundant elements. In this method, two PUF outputs are saved in the database to register a user. In authentication, the first PUF output in the database is just checked. The second PUF output in the database is only checked in the exceptional cases when the first PUF does not work correctly; therefore, both false reject rates and latencies are not degraded. A PW manager node is implemented using a low-cost microcontroller, SRAM PUF, and nonvolatile SRAM. The nonvolatile SRAM is embedded in the PWM node circuit as a local database. Statistical tests on the applied commercial SRAM in this article show better PUF quality than those used in previous research. Also, to handle the error in PUF responses, only the stable SRAM cells are used. This article presents the first prototype of a resilient PW manager node with an embedded local database to the best of our knowledge.

Simulations of single event effects in 6T2C-based ferroelectric non-volatile static random access memory

The single event effects (SEEs) on ferroelectric Hf0.5Zr0.5O2 capacitor-based non-volatile static random access memory (nvSRAM) were investigated by simulation. A nvSRAM cell integrated with two ferroelectric Hf0.5Zr0.5O2 capacitors is proposed in this study. A macro-model of the ferroelectric Hf0.5Zr0.5O2 capacitor, extracted from the real fabricated devices, is utilized for simulation analysis. Fundamental store and recall operations of the proposed nvSRAM design have been demonstrated. An independent double exponential current source was utilized and injected into specific circuit nodes to simulate the heavy ion induced single event transient current. The simulation results show that the transient pulse current is possible to upset the logic state of the memory cell from 1 to 0, but whether it can recover in a short time period after the upset errors depends on the exact value of linear energy transfer for the injected particles. In addition, increasing the remnant polarization (P r) and decreasing the coercive voltage (V c) and film thickness of ferroelectric capacitors can mitigate the influence of SEEs, which provides guidance for process hardening techniques aiming at space applications.