Nonvolatile SRAM Research Articles

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks.

Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up

This work presents a Non-Volatile SRAM (NV-SRAM) cell, resilient to information loss. The cell features fast storage (20ns) for the operating voltage of 1.0V. The information is backed-up during POWER-DOWN/RESTORE cycle in two bipolar Oxide Resistive RAMs (OxRRAMs). The proposed NV-SRAM is designed with an 8T2R structure using 22nm FDSOI technology and resistive memory devices based on HfO2. The stability and the reliability of the NV-SRAM cell is investigated by taking into account the variability of the transistors. It is shown that high ROFF/RON is necessary to ensure reliable RESTORE operation and high SRAM yield under cell area and power consumption constraints.

A 71%-Area-Reduced Six-Input Nonvolatile Lookup-Table Circuit Using a Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure

A single-ended circuit using three-terminal magnetic tunnel junction (3T-MTJ) devices is proposed for a compact nonvolatile lookup-table (NV-LUT) circuit. The use of 3T-MTJ devices makes a high tunnel magneto-resistance ratio used in the circuit, because read-current path is separated from the write-current path. By utilizing single-ended circuit structure, the NV-LUT circuit becomes quite simple without reference circuit. In fact, the effective area of the proposed 6-input NV-LUT circuit is only 29% the size of the corresponding CMOS-based implementation using two-terminal-MTJ-based nonvolatile static random access memory cells, with a simulation program with integrated circuit emphasis (SPICE) simulation under a 90 nm CMOS technology.

Circuit Implementation, Operation, and Simulation of Multivalued Nonvolatile Static Random Access Memory Using a Resistivity Change Device

We proposed and computationally analyzed a multivalued, nonvolatile SRAM using a ReRAM. Two reference resistors and a programmable resistor are connected to the storage nodes of a standard SRAM cell. The proposed 9T3R MNV-SRAM cell can store 2 bits of memory. In the storing operation, the recall operation and the successive decision operation of whether or not write pulse is required can be performed simultaneously. Therefore, the duration of the decision operation and the circuit are not required when using the proposed scheme. In order to realize a stable recall operation, a certain current (or voltage) is applied to the cell before the power supply is turned on. To investigate the process variation tolerance and the accuracy of programmed resistance, we simulated the effect of variations in the width of the transistor of the proposed MNV-SRAM cell, the resistance of the programmable resistor, and the power supply voltage with 180 nm 3.3 V CMOS HSPICE device models.

Memristor-Based Nonvolatile Random Access Memory: Hybrid Architecture for Low Power Compact Memory Design

In this paper, a new approach toward the design of a memristor based nonvolatile static random-access memory (SRAM) cell using a combination of memristor and metal-oxide semiconductor devices is proposed. Memristor and MOSFETs of the Taiwan Semiconductor Manufacturing Company's 180-nm technology are used to form a single cell. The predicted area of this cell is significantly less and the average read-write power is ~25 times less than a conventional 6-T SRAM cell of the same complementary metal-oxide semiconductor technology. Read time is much less than the 6-T SRAM cell. However, write time is a bit higher, and can be improved by increasing the mobility of the memristor. The nonvolatile characteristic of the cell makes it attractive for nonvolatile random access memory design.

Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications

Many mobile SoC chips employ a “two-macro” approach including volatile and nonvolatile memory macros (i.e. SRAM and Flash), to achieve high-performance or low-voltage power-on operation with the capability of power-off nonvolatile data storage. However, the two-macro approach suffers from slow store/restore speeds due to word-by-word serial transfer of data between the volatile and nonvolatile memories. Slow store/restore speeds require long power-on/off time and leave the device vulnerable to sudden power failure . This study proposes a resistive memory (memristor) based nonvolatile SRAM (or memristor latch) cell to achieve fast bit-to-bit parallel store/restore operations, low store/restore energy consumption, and a compact cell area. This resistive nonvolatile 8T2R (Rnv8T) cell includes two fast-write memristor (RRAM) devices vertical-stacked over the 8T, and a novel 2T memristor-switch, which provides both memristor control and SRAM write-assist functions. The write assist feature enables the Rnv8T cell to use read favored transistor sizing to prevent read/write failure at lower VDDs. We also fabricated the first macro-level memristor-based (or RRAM-based) nonvolatile SRAM. This 16 Kb Rnv8T macro achieved the lowest store energy and R/W VDDmin (0.45 V) of any nonvolatile SRAM or two-macro solution.

Evaluation and Control of Break-Even Time of Nonvolatile Static Random Access Memory Based on Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

The energy performance of a nonvolatile static random access memory (NV-SRAM) cell for power gating applications was quantitatively analyzed for the first time using the performance index of break-even time (BET). The NV-SRAM cell is based on spin-transistor architecture using ordinary metal–oxide–semiconductor field-effect transistors (MOSFETs) and spin-transfer-torque magnetic tunnel junctions (STT-MTJs), whose circuit representation of spin-transistor is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The cell is configured with a standard six-transistor SRAM cell and two PS-MOSFETs. The NV-SRAM cell basically has a short BET of submicroseconds. Although the write (store) operation to the STT-MTJs causes an increase in the BET, it can be successfully reduced by the proposed power-aware bias-control for the PS-MOSFETs.

Evaluation and Control of Break-Even Time of Nonvolatile Static Random Access Memory Based on Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

The energy performance of a nonvolatile static random access memory (NV-SRAM) cell for power gating applications was quantitatively analyzed for the first time using the performance index of break-even time (BET). The NV-SRAM cell is based on spin-transistor architecture using ordinary metal–oxide–semiconductor field-effect transistors (MOSFETs) and spin-transfer-torque magnetic tunnel junctions (STT-MTJs), whose circuit representation of spin-transistor is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The cell is configured with a standard six-transistor SRAM cell and two PS-MOSFETs. The NV-SRAM cell basically has a short BET of submicroseconds. Although the write (store) operation to the STT-MTJs causes an increase in the BET, it can be successfully reduced by the proposed power-aware bias-control for the PS-MOSFETs.

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

A novel nonvolatile static random access memory cell is proposed that consists of four transistors and two spin-transfer-torque magnetic tunnel junctions (STT-MTJs). In the case of the NFET driver cell, the free layers of the magnetic tunnel junctions are connected to the transistors' sources and drains to make the cell read-disturb free. The static power is totally eliminated as the power line is shut down during data hold. The static noise margin of the cell is calculated based on the experimental data on MTJ switching that is enhanced from the resistive load SRAM cell due to the MTJ's switching operation. The cell size is estimated to become smaller than the 6-transistor SRAM cell when it is designed at 45 nm node and beyond owing to the MTJ's area shrink as well as the thinning of its tunnel dielectrics (MgO).

Nonvolatile Static Random Access Memory Using Resistive Switching Devices: Variable-Transconductance Metal–Oxide–Semiconductor Field-Effect-Transistor Approach

In this paper, we present a variable-transconductance (gm) metal–oxide–semiconductor field-effect-transistor (VGm-MOSFET) architecture using a nonpolar resistive switching device (RSD) for nonvolatile bistable circuit applications. The architecture can be achieved by connecting an RSD to the source terminal of an ordinary MOSFET. The current drive capability of the VGm-MOSFET can be modified by resistance states of the connected RSD, which is a very useful function for nonvolatile bistable circuits, such as nonvolatile static random access memory (NV-SRAM) and nonvolatile flip-flop (NV-FF). NV-SRAM can be easily configured by connecting two additional VGm-MOSFETs to the storage nodes of a standard SRAM cell. Using our developed SPICE macromodel for nonpolar RSDs, successful circuit operations of the proposed NV-SRAM cell were confirmed.

Nonvolatile Static Random Access Memory Using Magnetic Tunnel Junctions with Current-Induced Magnetization Switching Architecture

We propose and computationally analyze a nonvolatile static random access memory (NV-SRAM) cell using magnetic tunnel junctions (MTJs) with magnetic-field-free current-induced magnetization switching (CIMS) architecture. A pair of MTJs connected to the storage nodes of a standard SRAM cell with CIMS architecture enables fully electrical store and restore operations for nonvolatile logic information. A wide range of tunneling magnetoresistance (TMR) ratios and Vhalf (the bias voltage when the TMR ratio is reduced to half its original value) values are acceptable for the operation of the proposed NV-SRAM cell. Successful operation can be easily achieved when moderate TMR and Vhalf values such as 100% and 100 mV, respectively, are used. The proposed NV-SRAM is expected to be a key component of next-generation power-gating logic systems with extremely low static-power dissipation.

Nonvolatile static random access memory based on spin-transistor architecture

The authors proposed and computationally analyzed nonvolatile static random access memory (NV-SRAM) architecture using a new type of spin transistor comprised of a metal-oxide-semiconductor field-effect transistor (MOSFET) and magnetic tunnel junction (MTJ) that is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit approach to reproduce the functions of spin transistors, based on recently progressed magnetoresistive random access memory technology. The proposed NV-SRAM cell can be simply configured by connecting two PS-MOSFETs to the storage nodes of a standard SRAM cell.

Development of an Abstract Model for a Non-volatile Static Random Access Memory

The capability to protect against power fluctuations, which eventually prevents the corruption of the memory contents makes non-volatile static random access memory a very good choice for use in highly reliability applications. These random access memories are protected against data writing in addition to preserving the desired contents. Energy source and control circuitries are embedded into it for achieving the same. The control circuitry constantly monitors supply voltage level, inhibits data corruption, and switches on the energy source once it falls beyond a threshold level. In this paper, development of an abstract model for such a non-volatile static random access memory chip has been presented. Test sequences based on this model have been generated for this memory chip. These test sequences have been implemented in VLSI tester and exercised on the chips.

Impact of Smoke Exposure on Digital Instrumentation and Control

Smoke can cause interruptions and upsets in active electronics. Because nuclear power plants are replacing analog with digital instrumentation and control systems, qualification guidelines for new systems are being reviewed for severe environments such as smoke and electromagnetic interference. Active digital systems, individual components, and active circuits have been exposed to smoke in a program sponsored by the U.S. Nuclear Regulatory Commission. The circuits and systems were all monitored during the smoke exposure, indicating any immediate effects of the smoke. The results of previous smoke exposure studies have been reported in various publications. The major immediate effect of smoke has been to increase leakage currents and to cause momentary upsets and failures in digital systems. This paper presents new results from conformal coatings, memory chips, and hard drive tests.The best conformal coatings were found to be polyurethane, parylene, and acrylic (when applied by dipping). Conformal coatings can reduce smoke-induced leakage currents and protect against metal loss through corrosion. However conformal coatings are typically flammable, so they do increase material flammability. Some of the low-voltage biased memory chips failed during a combination of high smoke and high humidity. Typically, smoke along with heat and humidity is expected during fire, rather than smoke alone. Thus, due to high sensitivity of digital circuits to heat and humidity, it is hypothesized that the impact of smoke may be secondary.Low-voltage (3.3-V) static random-access memory (SRAMs) were found to be the most vulnerable to smoke. Higher bias voltages decrease the likelihood of failure. Erasable programmable read-only memory (EPROMs) and nonvolatile SRAMs were very smoke tolerant. Failures of the SRAMs occurred when two conditions were present: high density of smoke and high humidity. As the high humidity was present for only part of the test, the failures were intermittent. All of the chips that failed during the test recovered after enough venting.Hard disks were tested in severe environments but did not fail during the 2 h of monitoring.While the results of the tests documented in this report confirm that digital circuits can indeed be vulnerable to smoke, there is currently no practical, repeatable testing methodology, so it is not feasible to assess smoke susceptibility as part of environmental qualification. As a result, the most reasonable approach to minimizing smoke susceptibility is to employ design, implementation, and procedural practices that can reduce the possibility of smoke exposure and enhance smoke tolerance. Traditional approaches to mitigate its effects in digital safety instrumentation and control, such as redundancy, separation, defense in depth, as well as adherence to standards (e.g., the Institute of Electrical and Electronics Engineers’ IEEE 384) and the Code of Federal Regulations Appendix R of 10 CFR 50, should continue to be applied.

NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors

This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A V/sub dd//2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies.

Electronic bistability in electrochemically self-assembled quantum dots: A potential nonvolatile random access memory

An electronic bistability has been observed in a two-dimensional spatially ordered array of 10 nm quantum dots self-assembled by electrodepositing CdS in nanoporous anodic alumite film. The current–voltage characteristic of the array shows switching between two stable conductance states, which can be controlled by an external bias. The bistability is observed when current flows laterally between two contacts on the top surface of the array, and also when current flows vertically between a top contact and the bottom (conducting) substrate. If the system is left in one conductance state, it remains there for at least 180 h and possibly much longer, until switched to the other state by an external bias. Such an effect may find applications in inexpensive, ultradense nonvolatile static random access memory.

Nonvolatile SRAM cellusing different capacitance loading

A simple and novel nonvolatile SRAM (NVSRAM) cell is proposed. The NVSRAM cell can be achieved by adding only one nonvolatile device with split floating gates to a conventional SRAM cell. It acts as a conventional SRAM cell under normal operation. SRAM cell data are programmed to the nonvolatile device by hot electron injection. At power up, data are restored using different capacitance loading resulting from the split floating gate. The operations have been confirmed by circuit simulation. The NVSRAM cell is symmetric, and therefore has better retention characteristics than other NVSRAM cells.

Some physical and technological aspects of designing of ferroelectric non-volatile SRAM

Modified scheme of the non-volatile memory cell for ferroelectric SRAM is proposed allowing an enhanced reliability and essential lowering of demands to the electrical properties of the ferroelectric capacitors (FECAPs). It is shown that the successful integration of sol-gel FECAPs into a Si-based CMOS technology is possible using the common lift-off and wet-etching photolithography. The FECAPs fatigue problem and its possible physical mechanisms are discussed.

Analysis, measurement, and simulation of dynamic write inhibit in an nvSRAM cell

Dynamic write inhibit (DWI) is a method of selectively inhibiting the programming (writing) of nonvolatile semiconductor memory cells. Its primary use is in silicon nitride oxide semiconductor (SNOS) and metal nitride oxide semiconductor (MNOS) memories, although it may be generalized to other nonvolatile technologies. This technique is based on a mechanism generally known as deep-depletion channel shielding (DDCS). A characterization of this phenomenon from the vantage points of analytic, experimental, and numerical simulations is presented. In addition, a brief review of the literature and the introduction of a novel memory cell used in a 64K nonvolatile static random access memory (nvSRAM) demonstrate the need for this better physical understanding.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>