Nonvolatile Memory Structure Research Articles

Effect of annealing on charge transfer in Ge nanocrystal based nonvolatile memory structure

Ge nanocrystals (nc-Ge) embedded in the gate oxide of the nonvolatile memory structure were synthesized by Ge ion implantation followed by thermal annealing at 800 °C for various durations. Large changes in the structural and chemical properties of the Ge+-implanted oxide have been observed, and they have been found to possess a significant impact on the charge transfer in the oxide layer. The distribution and concentration of the nc-Ge and dissolved Ge atoms which serve as both the charge storage and transfer sites in the oxide are affected by the annealing. Two charge transfer mechanisms, i.e., the lateral charge diffusion along the Ge-distributed layer and the charge leakage from the charge storage sites to the Si substrate via the charge transfer sites, have been identified based on the charge retention behaviors. Both mechanisms are enhanced by the annealing as a result of the change in the distribution and concentration of the charge transfer sites.

Mesoscopic phenomena in Au nanocrystal floating gate memory structure

A resonant tunneling process is demonstrated in the HfAlO/Au nanocrystals/HfAlO trilayer nonvolatile memory (NVM) structure on Si, where the electrons tunnel back and forth to the Au nanocrystals due to the various mesoscopic behaviors. The electron tunneling behavior in this trilayer structure exhibits dissimilar resemblance to those in double-barrier tunnel junctions taking into account of the correlation of Coulomb blockade effect. The observed specific tunneling process is beneficial in studying the interplays of various mesoscopic physics and application of single electron devices into NVM.

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Single electron tunneling and Coulomb blockade effect in HfAlO∕Au nanocrystals/HfAlO trilayer nonvolatile memory structure

Single electron tunneling and Coulomb blockade effect have been observed in the HfAlO∕Au nanocrystals/HfAlO trilayer floating gate nonvolatile memory structure. This trilayer floating gate memory structure exhibits a significant memory window, and resonant tunneling current peaks and Coulomb staircase are obtained at 20K low temperature. Compared to the ordinary single electron devices, this is the first time that a clear single electron tunneling oscillation has been observed in the floating gate memory structure. This resonant tunneling phenomenon in floating gate memory may open a door toward application as single electron device.

Scalable 3-D Fin-Like Poly-Si TFT and Its Nonvolatile Memory Application

In this paper, we extensively investigated the structure and electrical characteristics of an n-type poly-Si thin-film transistor with a novel 3D fin-like channel. Further, owing to the high-quality thin film in the channel, an experimental device with a nonvolatile (NV) memory structure for system integration on panel or embedded memory applications is successfully demonstrated for the first time. By following the previously reported method and by improving the process conditions, the final fin-like channel shows a real 3D profile and a maximum aspect ratio of 3.5:1 with a minimum average width equal to 135 nm after an excimer laser annealing on a unique prepatterned amorphous silicon channel. The high-level dc characteristics, such as carrier's field-effect mobility up to 289 cm2 /V.s, subthreshold slope below 190 mV/dec, ON-OFF current ratio greater than 5 x 106, etc., reveal the effect of film quality and the advantage of the gate-all-around structure on the device's performance; moreover, it also indicates one potential scaling method for this technology. By applying a special program/erase (P/E) mode with electron injection/expulsion from the backside gate electrode, the NV memory structure in this channel demonstrates reasonable P/E characteristics, threshold voltage shifting of 1.41 V at | Vg = 12 V, pulse time = 1 ms, and acceptable reliability.

Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure

In this work, we study a polycrystalline silicon thin-film transistor (poly-Si TFT) combined with a silicon–oxide–nitride–oxide–silicon (SONOS) stack gate dielectric and nanowire channels structure for the applications of transistor and nonvolatile memory. The proposed device named with NW SONOS-TFT has superior electrical characteristics of transistor and also can exhibit high program/erase (P/E) efficiency under adequate bias operation. The V th decreases from 2.45 V to 1.76 V and subthreshold swing reduces from 0.57 V/decade to 0.42 V/decade. The programming V th shift is improved from 2.2 V to 3.3 V at 14 V for 1 s and the erasing V th shift is improved from − 0.3 V to − 1.3 V at − 14 V for 1 s. The dramatic improvement can be attributed to the tri-gate structure and corner effect. In addition, the memory device has a promising data retention behavior at 85 °C and a 0.8 V memory window after 5 × 10 3 P/E cycles operations. Hence, the NW SONOS-TFT is suitable for application in the future system-on-panel display.

Modeling and simulation for the enhancement of electron storage in a stacked multilayer nanocrystallite silicon floating gate memory

In this article, we investigate the storage enhancement mechanism of stacked multilayer nanocrystallite silicon (nc-Si) structures in a master-equation-based equivalent circuit model. As a theoretical extension from our previous experimental works, we reveal the detail injection sequence of electrons into the multilayer nc-Si structure via a direct tunneling process, and how the retention property is enhanced by the stacked structures. Seeking a further improvement in the multilayer nc-Si-based nonvolatile memory structure, we compare two major approaches for that purpose, i.e. (1) by further increasing the number of stacked layers or (2) by adopting an asymmetric double-layer structure. It is shown that the latter is more promising for achieving better nonvolatile storage property and shows a more effective threshold shifting, while retaining the virtues of direct tunneling process like fast write/erase and low operation voltage. We suggest that these results provide important guides for practical design of memory devices based on multilayer nc-Si floating gate structures.

Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods

This paper presents an experimental comparison of dummy cell extraction methods of the gate capacitance coupling coefficient for floating gate non-volatile memory structures from different geometries and technologies. These results show the significant influence of mismatching floating gate devices and reference transistors on the extraction of the gate capacitance coupling coefficient. In addition, it demonstrates the accuracy of the new bulk bias dummy cell extraction method and the importance of the β function, introduced recently in [Duane R, Beug F, Mathewson A. Novel capacitance coupling coefficient measurement methodology for floating gate non-volatile memory devices. IEEE Electr Dev Lett 2005;26(7):507–9], to determine matching pairs of floating gate memory and reference transistor.

Charging/discharging kinetics in LPCVD silicon nanocrystal MOS memory structures

The paper focuses on the peculiarities of charging/discharging kinetics and write/erase (W/E) window formation in nanocrystal metal-oxide semiconductor (MOS) non-volatile memory (NVM) structures prepared by low-pressure chemical vapor deposition (LPCVD) of amorphous silicon, followed by solid phase crystallization and thermal oxidation. It is generally known that the W/E window formation via pulse injection depends on the kinetics of carriers trapping (electrons and/or holes) in the nanocrystal NVM structure and consequently on the cumulative time of recharging bias application, i.e. pulse duration and number of applied pulses. In this work, we have shown that with the same cumulative time biasing but different charging pulse durations, the resulting W/E window width can be rather different, demonstrating a staircase window formation. This phenomenon is interpreted by a model of partial fast charge draining from the trapping sites in the vicinity of Si nanoclusters into the Si substrate. The detailed experimental investigation of charging/discharging kinetics of the considered structures in combination with computer simulations lead to the conclusion that there is a single process of negative charge trapping with a time constant of 235±35 ms and at least four processes of positive charge trapping with time constants distributed in the range from <10 ms to >10 s.

Nanoscale floating-gate characteristics of colloidal Au nanoparticles electrostatically assembled on Si nanowires

Nanoscale floating-gate characteristics of colloidal Au nanoparticles electrostatically assembled on Si nanowires have been investigated. Colloidal Au nanoparticles with ∼5nm diameters were selectively deposited onto the lithographically defined n-type Si nanowire surface by 2min electrophoresis between the channel and the side gates. The device transfer characteristics measured at room temperature showed hysteresis, with the depletion mode cutoff voltage applied by the side gates shifted by as much as 1.5V, with the source-drain bias at 1.4V. The results demonstrate that the electrostatic assembly of colloidal Au nanoparticles is a useful method for the fabrication of Si nanowire based nanoscale floating-gate nonvolatile memory structures.

Pd-nanocrystal-based nonvolatile memory structures with asymmetric SiO2∕HfO2 tunnel barrier

Pd nanocrystals (NCs) on asymmetric tunnel barrier (ATB) composed of stacked SiO2 and HfO2 layers have been employed for nonvolatile memory devices. The Pd-NC layers are formed by electrostatic self-assembly of negatively charged colloidal Pd NCs. The presence of isolated Pd NCs of ∼5nm embedded in HfO2 is confirmed by scanning and transmission electron microscopy images. Outstanding program∕erase (P∕E) properties from C-V curves are observed with a memory window of 6V under ±17V. Extrapolation of the data up to ten years shows that the flatband voltage drops at the P∕E levels are maintained within only 1.0∕0.5V, respectively, resulting from the efficient data retention based on the ATB. These results are promising enough for the memory structure to be utilized for the multilevel charge storage.

Novel Structures for a 2-Bit per Cell of Nonvolatile Memory Using an Asymmetric Double Gate

A 2-bit operational metal/silicon-oxide-nitride-oxide-silicon (MONOS/SONOS) nonvolatile memory using an asymmetric double-gate (ASDG) MOSFET was studied to double flash memory density. The 2-bit programming and erasing was performed by Fowler-Nordheim (FN) tunneling in a NAND array architecture using individually controlled gates. A threshold voltage shift of programmed states for the 2-bit operation was investigated with the aid of a SILVACO® simulator in both sides of the gate by changing gate workfunctions and tunneling oxide thicknesses. In this paper, the scalability of the device down to 30 nm was demonstrated by numerical simulation. Additionally, guidelines of the 2-bit ASDG nonvolatile memory (NVM) structure and operational conditions were proposed for program, read, and erase.

Effects of forming gas annealing on the memory characteristics of Ge nanocrystals embedded in LaAlO 3 high- k dielectrics for flash memory device application

Forming gas (FG) annealing effects of a nonvolatile flash memory structure using Ge nanocrystals (NCs) floating gate embedded in LaAlO 3 high- k tunneling/control oxide were studied. Atomic force microscopy and high-resolution transmission electron microscopy measurements revealed that the pulsed-laser deposited Ge NCs were well self-organized and the average diameter of the sphere-like NCs was around 6 nm. By using a double sweep capacitance–voltage measurement, memory windows of 1.4 and 1.0 V were obtained for the as-deposited and FG annealed samples, respectively. The charge loss rate of the FG annealed sample was lower than that of the as-deposited sample, and this could be explained by the decrease of defects in the dielectrics and Ge NCs as well as their interfacial states that may have acted as charge leak channels.

Metal Nanocrystal Memory With High-&amp;lt;tex&amp;gt;$kappa$&amp;lt;/tex&amp;gt;Tunneling Barrier for Improved Data Retention

A nonvolatile memory (NVM) with metal nanocrystal (NC) embedded in high-/spl kappa/ dielectrics is proposed. With the larger work function of the metal NC compared to that of silicon NC, the metal NC memory exhibits the better data retention characteristic. The theoretical analysis showing the effect of the electron barrier height on tunneling current density is also presented to support the importance of work function engineering of the NC in NVM structure. The other electrical characteristics such as the programming transient and data endurance are also studied and described in this paper.

Electrical study of Ge-nanocrystal-based metal-oxide-semiconductor structures for p-type nonvolatile memory applications

Nonvolatile memory structures using Ge nanocrystals embedded in SiO2 have been characterized by room and low temperature current–voltage and capacitance–voltage measurements. The Ge nanocrystals have been fabricated by low pressure chemical vapor deposition process which is shown to be well suited for a real control of the tunnel oxide thickness. The deposition conditions allow a separate control of nc-Ge density and size. Using capacitance–voltage characterizations on nonvolatile memory structures, we have measured the charging and discharging kinetics of holes for tunnel oxides in the range 1.2–2.5 nm. Using current–voltage measurements and simulations, we have also shown that nc-Ge are at the origin of a tunnel-assisted current. Simulations have demonstrated that the hole’s charging effects strongly reduce the current density across the nonvolatile memory structure. Combined with a good control of nc-Ge properties, the use of Ge dots with large diameters (&amp;gt;10 nm) seems to be a promising way for p-type memory applications.

A Novel MONOS-Type Nonvolatile Memory Using High-&amp;lt;tex&amp;gt;$kappa$&amp;lt;/tex&amp;gt;Dielectrics for Improved Data Retention and Programming Speed

This paper presents a novel metal-oxide-nitride-oxide-silicon (MONOS)-type nonvolatile memory structure using hafnium oxide (HfO/sub 2/) as tunneling and blocking layer and tantalum pentoxide (Ta/sub 2/O/sub 5/) as the charge trapping layer. The superiorities of such devices to traditional SiO/sub 2/-Si/sub 3/N/sub 4/-SiO/sub 2/ stack devices in obtaining a better tradeoff between faster programming and better retention are illustrated based on a band engineering analysis. The experimental results demonstrate that the fabricated devices can be programmed as fast as 1 /spl mu/s and erased from 10 ns at an 8-V gate bias. The retention decay rate of this device is improved by a factor more than three as compared to the conventional MONOS/SONOS type devices. Excellent endurance and read disturb performance are also demonstrated.

Scaling of flash NVRAM to 10's of nm by decoupling of storage from read/sense using back-floating gates

Conventional floating-gate flash memory structures have limited scalability due to nonscaling of insulators for charge retention and reliability, inefficiency of hot-electron injection processes at nanometer dimensions due to off-equilibrium overshoot effects, poor short-channels effects due to poor electrostatics and large voltages needed at the control/read gate as a result of voltage leveraging. We present and analyze a new nonvolatile memory structure based on back-floating gate, which decouples the read/sensing from storage/programming and thus allows a design with efficient storage and improved injection and short-channel characteristics. This structure can be scaled to dimensions similar to that of high performance transistors, i.e., 10's of nanometers, without compromising the requirements of insulator thickness. Characteristics of the structure are analyzed using coupled simulation and modeling that employs Monte Carlo simulation for hot carrier analysis and quasistatic calculation for evaluating charge injection and storage. We compare the characteristics of the new structure with conventional structures and their use as a memory cell.

Electron injection characteristics of MNOS nonvolatile semiconductor memory structure using the reverse breakdown of the PN junction

AbstractIn this paper, we describe an improved carrier injection method for the metal nitride‐oxide semiconductor (MNOS) structure, which is a prospective nonvolatile semiconductor memory device. The investigation is based on the prediction that carrier injection should be improved by increasing the carrier density at the Si surface and by lowering the tunneling barrier height of the SiO2 and that these conditions should be realizable by using the current flow due to reverse breakdown of the pn junction near the channel region of the Si surface under the gate electrode.Experiments indicate that the flatband voltage shift in the presence of electron injection is large as a result of the reverse breakdown current of the pn junction. Electron injection was further improved by an additional lowering of the tunneling barrier height associated with the voltage drop across the resistance connected to the bias circuit of the pn junction. This voltage drop was produced by the current flow due to reverse breakdown of the pn junction.Faster, stronger carrier injection from the Si surface to the traps in the insulator of MNOS structure can be realized by optimizing the doping densities in p and n regions and optimizing the resistance connected to the pn biasing circuit. This method is useful for electrical erasable nonvolatile semiconductor memory (EEPROM) devices without voltage up‐converter circuits.

Amphoteric trap modeling of multidielectric scaled SONOS nonvolatile memory structures

We have characterized multidielectric scaled SONOS nonvolatile memory structures with the quasi-static linear voltage ramp (LVR) technique and dynamic pulse measurements. We have formulated physically-based ERASE/WRITE and retention methods with deep level amphoteric traps which capture and emit carriers to the bands in the silicon nitride film. Amphoteric trap parameters are extracted by the LVR technique. ERASE/WRITE and retention amphoteric trap model simulations agree well with the experimental dynamic pulse measurements. Experimental scaled SONOS structures have been fabricated with tunnel oxide X OT=20 Å, nitride X N=30 Å and blocking oxide X OB=55 Å and demonstrated a static flatband shift of 3.6 V with ±5 V programming voltages. These structures may be used as the nonvolatile memory element in high density VLSI circuits.

Charge centroid in MIOS nonvolatile memory structures

The experimental charge-centroid relations in MNOS, MAOS (A = Al 2 O 3 ), and MANOS nonvolatile memory structures were analyzed and compared. New data on trap density, trapping length, and capture cross section for Al 2 O 3 and Si 3 N 4 were derived from these measurements. The trapping length in Al 2 O 3 is about 5 times larger than in Si 3 N 4 . The charge-detrapping rate in Al 2 O 3 is smaller than in Si 3 N 4 . The experimental charge-centroid relation during charge trapping and charge detrapping is described by two expressions which include the capture cross section as the only physical parameter. The calculated capture cross section is constant for MNOS and also during charge trapping in MAOS, but decreases linearly with propagating centroid position after onset of charge detrapping within Al 2 O 3 . Trap-assisted tunneling over multiple deep trap levels in Al 2 O 3 is proposed to interpret the results for MAOS. Oxygen annealing of Al 2 O 3 enhances storage capability of injected negative charge within the lower bandgap Si 3 N 4 region of the MANOS structure. This behavior is related to blocking of detrapped nitride charge at the oxygen densified energy barrier created at the Si 3 N 4 - Al 2 O 3 boundary.