Nonvolatile Memory Structure Research Articles

Electric-polarization-driven magnetic phase transition in a ferroelectric–ferromagnetic heterostructure

Magnetoelectric coupling is of great interest recently to both understand the fundamental physics and device applications. Materials with strong magnetoelectric coupling, high Curie temperature, and large electric polarization are still rare. We suggest a heterostructure that combines the known memory effect of the switchable ferroelectric In2Se3 [Adv. Funct. Mater. 2019, 29, 1808606] with a van der Waals bonded two-dimensional (2D) metal-organic framework (MOF) film. The magnetic ground state of this MOF can be changed from an antiferromagnetic state to a ferromagnetic through hole-doping. We use first-principles calculations to show that in such a heterostructure, adequate doping differences to cause this phase transition are expected from the changes in the interfacial charge transfer between the MOF and In2Se3 when the polarization direction of the In2Se3 is reversed. This and similar 2D heterostructures may, therefore, provide both a fascinating material platform for understanding the fundamental physics of magnetoelectric coupling and a strategy for designing spin-current-based nonvolatile memory structures.

Engineering an Indium Selenide van der Waals Interface for Multilevel Charge Storage.

As the continuous miniaturization of floating-gate transistors approaches a physical limit, new innovations in device architectures, working principles, and device materials are in high demand. This study demonstrated a nonvolatile memory structure with multilevel data storage that features a van der Waals gate architecture made up of a partially oxidized surface layer/indium selenide (InSe) van der Waals interface. The key functionality of this proof-of-concept device is provided through the generation of charge-trapping sites via an indirect oxygen plasma treatment on the InSe surface layer. In contrast to floating-gate nonvolatile memory, these sites have the ability to retain charge without the help of a gate dielectric. Together with the layered structure, the surface layer with charge-trapping sites facilitates continual electrostatic doping in the underlying InSe layers. The van der Waals gating effect is further supported by trapped charge-induced core-level energy shifts and relative work function variations obtained from operando scanning X-ray photoelectron spectroscopy and Kelvin probe microscopy, respectively. On modulating the amount of electric field-induced trapped electrons by the electrostatic gate potential, eight distinct storage states remained over 3000 s. Moreover, the device exhibits a high current switching ratio of 106 within 11 cycles. The demonstrated characteristics suggest that the engineering of an InSe interface has potential applications for nonvolatile memory.

Low Power Magnetic Non-volatile Flip-Flops with Self-Time Logical Writing for High-End Processors

Presently, leakage in a complementary metal oxide semiconductor (CMOS) increases due to high static power dissipation during reading and writing operations. Spin transfer torque magnetic random access memory is seen as the most reassuring non-volatile memory structure to overcome the current problem of static power dissipation. In conventional techniques, magnetic flip-flop (MFF) consumes large power and static current dissipation due to conditional-based single circuitry, which can be optimized through introduction of MFF with the combination of low swing conditional capture edge-trigged flip-flop, self-time logical writing circuit, and coarse-grain-based power gating circuit. This method has been developed particularly for high-precision, high-speed, mixed-mode application-specific integrated circuits; the reduction in total power consumption, static current, and PDP shows the proposed technique that as highly suitable for low power applications in high-end processors, using nanoscale technology. In this research work, results have been validated by simulations and measurements using 180 nm CMOS technology, tested using 1.8 v supply voltage.

Band-alignment dominated retention behaviors in high-k composite charge-trapping memory devices

A nonvolatile memory structure with a high-k composite of ZnO-TiO2 as a charge-trapping dielectric was fabricated by using rf-sputtering and atomic layer deposition techniques, in which the potential of the conduction-band minimum of the composite was designed to be lower than that of Si by the use of the special energy-band offsets among Si, ZnO, and TiO2. Compared to the conduction-band minimum of Si, a relatively negative potential of the high-k composite leads to a continuous rise in the shift of the flat-band potential of the memory device except a drop at the beginning part of the time-dependent retention curve after a programming operation. The drop was attributed to the escape of trapped charges at the Si/Al2O3 interface. After extracting the contribution to the deterioration of the retention curve from the traps at the Si/Al2O3 interface, it was identified that the band alignment in a charge-trapping memory device dominated its retention behaviors.

Towards an optical switching of memory effect in Au/TiO2/ITO/ZnO:Al/p-Si heterostructure based on nanoparticles

We have successfully realized a nonvolatile resistive memory structure by rf-magnetron sputtering technique using nanoparticles synthesized by sol–gel method. The resistive switching (RS) related to the Au/TiO2 Schottky contact was grafted on a photosensitive structure ITO/ZnO:Al/p-Si allowing memory effect switching optically activated. The RS takes place via tunneling path through potential barrier located at the Au/TiO2 interface. The memory effect persists under illumination and the Arrhenius plot of the surface of the V–I cycle shows an activation energy of about 160 meV in dark and 100 meV under visible illumination. This behavior of the RS optically activated is closely related to the electronic states in the Au/TiO2 interface which leads to perform an optical switching of the memory effect with the presented structure.

Role of annealing temperature on charge storage characteristics of Au nanocrystals with HfO2 tunneling and blocking layers

In this paper, we demonstrate the fabrication and charge storage characteristics of Au nanocrystals located between two hafnium oxide films acting as the tunneling and blocking layers serving as nonvolatile memory structure. The structure, composition and electrical properties of the device are drastically affected by annealing temperature. The inter-diffusion and stoichiometric changes of various layers are investigated using X-ray Photoelectron Spectroscopy and Rutherford Backscattering Spectroscopy. Electrical measurements show an improvement in leakage characteristics with annealing. The C-V hysteresis loop with and without Au nanocrystals are compared to understand charge storage behavior of the device structures. The occurrence of well-defined hysteresis loop with Au nanocrystals indicates significant role of Au nanocrystals in charge storage characteristics of the device.

Thermoelectric La-doped SrTiO3 epitaxial layers with single-crystal quality: from nano to micrometers

High-quality thermoelectric La0.2Sr0.8TiO3 (LSTO) films, with thicknesses ranging from 20 nm to 0.7 μm, have been epitaxially grown on SrTiO3(001) substrates by enhanced solid-source oxide molecular-beam epitaxy. All films are atomically flat (with rms roughness < 0.2 nm), with low mosaicity (<0.1°), and present very low electrical resistivity (<5 × 10−4 Ω cm at room temperature), one order of magnitude lower than standard commercial Nb-doped SrTiO3 single-crystalline substrate. The conservation of transport properties within this thickness range has been confirmed by thermoelectric measurements where Seebeck coefficients of approximately –60 μV/K have been recorded for all films. These LSTO films can be integrated on Si for non-volatile memory structures or opto-microelectronic devices, functioning as transparent conductors or thermoelectric elements.

Comparison of Physical and Electrical Characteristics of Memory Devices with NiO2 Charge Trapping Layer

In this study, a metal-oxide-high-k-oxide-silicon (MOHOS)-type nonvolatile memory structure using a high-k NiO2 film as the charge trapping layer is reported for nonvolatile memory application. We employ Rapid Thermal Annealing (RTA) to improve overall memory characteristics of the devices. We use structural and electrical analysis to study the performance of the devices. The crystalline structures and morphological features of NiO2 films were studied using atomic force microscopy and x-ray diffraction measurements. The fabrication of the MOHOS memory structure using NiO2 charge trapping layer is started with single-crystal 4-inch n-type silicon (100) wafers were cleaned using a standard RCA process. First, a thin 3nm SiO2 was thermally grown by dry oxidation furnace system at 850°C. Then, a 15 nm NiO2 trapping layer was deposited by RF sputtering with pure nickel target (99.99% pure) with argon (20 sccm) and oxygen (5 sccm) mixture ambient. Next, the wafers were annealed to form NiO2 charge trapping layer at different temperatures by rapid thermal annealing (RTA) in nitrogen ambient for 30s at 600°C, 700°C,800°C and 900°C. Then a 20nm SiO2 film was deposited as blocking oxide layer by plasma enhanced chemical vapor deposition (PECVD). After deposition blocking oxide layer, the sample was deposited 300nm aluminium (Al) film by thermal evaporator followed by patterning the gate by lithography and wet etching. Finally, a 300nm thick Al was deposited by thermal evaporator on the backside to form metal contact. Compared to the as deposited film, NiO2 film annealed at 900°C exhibited superior memory characteristics, such as a higher window of capacitance-voltage hysteresis loop, a larger flat-band voltage shift, and a lower charge loss rate at room temperature. These improvements might be attributed to the well-crystallized structure formation in the NiO2 with high trap density. Further, program/erase speed of the MOHOS structure has increased owing to larger flat-band shift. Samples with higher temperature annealing shows better charge retention (11%) owing to the reduction of local defects. We also studied charge retention at different temperature of 55°C and 85°C. We also utilize Arrhenius plots for shallow trap and deep trap fitting and activation energy of 0.18eV are extracted from the straight line. The endurance of the NiO2 MOHOS structure has measured using programming voltage of 13V for 1s and erasing voltage of -18V for 1s. NiO2 sample with 900°C RTA treatment can sustain the memory window of 2.4 V after 104 program/erase cycles. High temperature annealing improves the crystalline structure and strengthens the structure of trapping layer and resist the defect that produced during repeated program and erase cycle. In this study, the memory device NiO2 trapping layer with 20nm blocked oxide and annealed at 900℃ can improve memory device performance, including larger C-V hysteresis, better data retention, better endurance and smaller charge loss of about 11% at 25°C. Therefore, NiO2 trapping layer with proper annealing is very promising for MOHOS nonvolatile memory applications

Graphene-Based STT-RAM Cell With Improved Switching for Scaled Technology Nodes

Spin-transfer torque random-access memory (STT-RAM) is a nonvolatile, scalable, and fast memory structure, which benefits from high endurance and relatively low power consumption. However, there are some challenges in designing STT-RAM such as the tradeoff between decreasing the write current and the retention time. Increasing the write voltage as the cell size is scaled down is another challenge for STT-RAM due to the increasing resistance of its magnetic tunnel junction (MTJ). In this paper, a novel STT-RAM cell structure with a graphene-based spin filter including three graphene layers as MTJ is proposed for sub-20 nm technology nodes (e.g., 14 nm and beyond). By flowing a small (e.g., $3~\mu \text{A}$ ) and short width current pulse (e.g., 1 ns) through the center graphene layer, a reduction of 69% in the amplitude of the intrinsic switching current density (38% less than the predicted value for the conventional in-plane STT-RAM) is achieved without any penalty of data retention time for an 8 nm technology node. Furthermore, by flowing current through the center graphene layer, the intrinsic switching voltage of the proposed structure is decreased by 27%, 51%, and 59% for 14, 10, and 8 nm widths of the MTJ, respectively. The behavior of the proposed structure in a fast (precessional) switching mode (switching time less than 3 ns) is evaluated. Consequently, a reduction of 38% in the switching current density and the switching voltage can be attained for the 8 nm technology node, using the proposed idea. Simulation results are obtained using an object-oriented micromagnetic framework.

Quantum Dot Channel (QDC) Field Effect Transistors (FETs) and Floating Gate Nonvolatile Memory Cells

This paper presents silicon quantum dot channel (QDC) field effect transistors (FETs) and floating gate nonvolatile memory structures. The QDC-FET operation is explained by carrier transport in narrow mini-energy bands which are manifested in an array of SiOx-cladded silicon quantum dot layers. For nonvolatile memory structures, simulations of electron charge densities in the floating quantum dot layers are presented. Experimental threshold voltage shift in ID–VG characteristics is presented after the ‘Write’ cycle. The QDC-FETs and nonvolatile memory due to improved threshold voltage variations by incorporating the lattice-matched II–VI layer as the gate insulator.

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and depletion in response to polarization reversal in the barrier. The tunneling electrons should experience an extra barrier as long as the semiconductor surface is toggled to depletion, leading to a colossal tunneling electroresistance (Fig. 1). Wen and colleagues epitaxially deposited a 3-nm-thick ultrathin BaTiO3 film with an atomically smooth surface on a Nb-doped SrTiO3 oxide semiconductor and then deposited Pt electrodes on top to form Pt/BaTiO3/Nb:SrTiO3 tunnel junctions. These prototype devices show a tunneling electroresistance two orders greater than the best value ever reported in FTJs. The colossal ON/OFF ratio, low operation voltage (3 V for write and 100 mV for read), reliable switching reproducibility and long data retention suggest great potential for nondestructive readout nonvolatile memories. Moreover, the team observed that the tunneling resistance could be modulated continuously by applying voltage pulses with increasing amplitude due to the continuous tuning on the domain structure in the barrier. This novel FTJ can actually function as a memristor, the adaptive circuit element theoretically predicted 40 years ago but discovered only very recently. The use of memristors may pave the way to future neuromorphic computational architectures. The work by Wen and colleagues not only proposes a promising nonvolatile memory structure with potential to overcome semiconductor devices based on charge storage, but provides tremendous opportunities for innovation in nanoelectronics also.

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

This paper describes the use of II–VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeOx-cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II–VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrodinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

Mechanism of resistive switching in Cu/AlOx/W nonvolatile memory structures

The mechanism for resistive switching in aluminum oxide (AlOx) based electrochemical metallization memory cells is presented. Copper/AlOx/tungsten (Cu/AlOx/W) cells show reproducible resistive switching with an ON/OFF ratio of about 5 × 102 at a reading voltage of 0.1 V and reliable retention characteristics. Resistive switching occurs due to the formation and rupture of a Cu filament between the active electrode (Cu) and the counter electrode (W). The conduction of the devices was explained through back-to-back Schottky contacts in the OFF state, while it exhibits ohmic behavior in the ON state. Thermionic emission model was used to calculate the barrier heights of the Schottky contacts. The rupture of the Cu filament proved to occur at the weakest point of the filament inside the AlOx. Using Ohms Law, the slope of the linear I-V characteristics in the ON state was used to extract the Cu filament resistance and its diameter was estimated to be between 6 and 23 nm.

Effect of location of Si or Ge nanocrystals on the memory behavior of MNOS structures

Charge injection and retention behaviors of metal-nitride-oxide-silicon (MNOS) memory structures with Si or Ge nanocrystals embedded at a depth of 3nm in the nitride layer were studied. The effect of Si nanocrystals on these properties was opposite in comparison with that of Ge nanocrystals. To understand the origin of these opposite effects, the influence of the oxide thickness and of the depth, size and location of semiconductor nanocrystals has been studied on the charging behavior of MNOS non-volatile memory structures by the calculation of electron and hole tunneling probabilities, and by the simulation of memory window, memory hysteresis and retention behavior.For MNOS structures it is obtained that the presence of nanocrystals enhances the charge injection resulting in better performance, but only for structures with thin tunnel oxide layer (below 3nm), and if the nanocrystals are located close to the oxide/nitride interface. In the case of very high tunneling probability, i.e., of high tunneling currents the system approaches equilibrium and the memory behavior collapses. There is a narrow range of oxide thickness or depth of nanocrystals, where the charging properties change very fast. Retention exhibits a very sharp dependence on the oxide thickness and on depth of nanocrystals as well. Most part of the experimental results can be explained on the basis of the results of simulations.

Charging behavior of silicon nitride based non-volatile memory structures with embedded semiconductor nanocrystals

The charging behavior of MNS (metal-nitride-silicon) and MNOS (metal-nitride-oxide-silicon) structures containing Si or Ge nanocrystals were studied by capacitance–voltage (C–V) and memory window measurements and by simulation. Both the width of hysteresis of C–V characteristics and the injected charge exhibited exponential dependence on the charging voltage at moderate voltage values, while at high voltages the width of hysteresis of C–V characteristics and the injected charge exhibited saturation. The memory window for reference MNS structure without nanocrystals was wider than that for reference MNOS structures. The presence of nanocrystals enhanced the charging behavior of MNOS structures, but in MNS structures nanocrystals exhibited the opposite effect. The main conclusion is that the presence of nanocrystals or other deep levels close to the Si surface enhances the charge injection properties due to the increased tunneling probability, but nanocrystals or other deep levels located far from the Si surface in the nitride layer do not enhance, but even can degrade the charging behavior by the capture of charge carriers.

Ge-Doped Hafnia-Based Dielectrics for Non-Volatile Memory Applications

Fully high-k based non-volatile memory structures were fabricated by RF magnetron sputtering technique. The pure HfO2 and HfSiO materials were used as tunnel and/or control layers, whereas HfGeO ones were used as a charge storage node. The capacitance-voltage measurements of HfO2/HfGeO/HfO2 and HfSiO/HfGeO/HfSiO stacks were performed to study the charge trapping characteristics of these structures. The memory effect was observed in both types of MIS capacitors and the optimal annealing treatment was found to be at 610°C for 15 minutes. A memory window of ~7 V at a sweeping voltage of ± 14 V has been achieved, indicating the potential use of these stack structures for non-volatile memory devices.

Silicon Nanoclusters Embedded into Oxide Host for Non-Volatile Memory Applications

Non-volatile memory structures with embedded silicon nanoclusters were fabricated by RF magnetron sputtering approach. The capacitance-voltage characteristics of classical SiO2/Si-ncs-SiO2/SiO2 and HfO2/Si-ncs-SiO2/SiO2 structures have been compared. The specific deposition conditions and annealing treatment allowed a large memory window of about 6.8 V at a sweeping voltage of ± 6 V to be achieved. It was observed that the similar memory capacitance can be obtained for classical SiO2/Si-ncs-SiO2/SiO2 structures using multilayer charge storage node. The analysis of microstructural properties of the samples revealed that an annealing at 1000-1100°C results in the formation of crystallized silicon clusters, while the crystallization of HfO2 occurred with a tetragonal phase. It was also revealed that an annealing treatment at 950°C, at which amorphous Si clusters are formed, allowed a highest memory window to be obtained. This result indicates the benefit of low thermal budget treatment for low operating voltage non-volatile memory devices.

Integration of Self-Assembled Redox Molecules in Flash Memory Devices

Self-assembled monolayers (SAMs) of either ferrocenecarboxylic acid or 5-(4-Carboxyphenyl)-10,15,20-triphenyl-porphyrin-Co(II) (CoP) with a high- dielectric were integrated into the Flash memory gate stack. The molecular reduction-oxidation (redox) states are used as charge storage nodes to reduce charging energy and memory window variations. Through the program/erase operations over tunneling barriers, the device structure also provides a unique capability to measure the redox energy without strong orbital hybridization of metal electrodes in direct contact. Asymmetric charge injection behavior was observed, which can be attributed to the Fermi-level pinning between the molecules and the high- dielectric. With increasing redox molecule density in the SAM, the memory window exhibits a saturation trend. Three programmable molecular orbital states, i.e., CoP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup> , CoP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-</sup> , and CoP <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2-</sup> , can be experimentally observed through a charge-based nonvolatile memory structure at room temperature. The electrostatics is determined by the alignment between the highest occupied or the lowest unoccupied molecular orbital (HOMO or LUMO, respectively) energy levels and the charge neutrality level of the surrounding dielectric. Engineering the HOMO-LUMO gap with different redox molecules can potentially realize a multibit memory cell with less variation.

GENERAL SPICE MODELS FOR MEMRISTOR AND APPLICATION TO CIRCUIT SIMULATION OF MEMRISTOR-BASED SYNAPSES AND MEMORY CELLS

Memristor had been first theorized nearly 40 years ago by Prof. Chua, as the fourth fundamental circuit element beside the three existing elements (Resistor, Capacitor and Inductor) but because no one has succeeded in building a memristor, it has long remained a theoretical element. Some months ago, Hewlett-Packard (hp) announced it created a memristor using a TiO2/TiO2-X structure. In this paper, the characteristics, structures and relations for the invented hp's memristor are briefly reviewed and then two general SPICE models for the charge-controlled and flux-controlled memristors are introduced for the first time. By adjusting the model parameters to the hp's memristor characteristics some circuit properties of the device are studied and then two important memristor applications as the memory cell in a nonvolatile-RAM structure and as the synapse in an artificial neural network are studied. By utilizing the introduced models and designing the appropriate circuits for two most important applications; a nonvolatile memory structure and a programmable logic gate, circuit simulations are done and the results are presented.

Nonvolatile memory characteristics of atomic layer deposited Ru nanocrystals with a SiO2/Al2O3 bilayered tunnel barrier

This paper reports a formation process and electrical properties of a nonvolatile memory structure with atomic layer deposited Ru nanocrystals and a SiO2/Al2O3 bilayered tunnel barrier. Al2O3 tunnel barrier/Ru nanocrystals/Al2O3 blocking barrier were deposited sequentially on a SiO2 2 nm/Si substrate by an in situ atomic layer deposition (ALD) process. Ru nanocrystals grown on the Al2O3 surface for 80 ALD cycles had a spatial density of 2.4×1012 cm−2 and an average diameter of 2.6 nm (38% standard deviation in the diameter). Charging/discharging behavior of the Ru nanocrystals embedded in the metal-oxide-semiconductor capacitor structure was examined by programming/erase operations and comprehended in terms of asymmetric barrier height of the bilayered tunnel barrier. The memory structure showed charge retention of 91% and 85% after 105 s at room temperature and at 85 °C, respectively.