Nonvolatile Semiconductor Memory Research Articles

Research on Improved Crystallization Properties and Underlying Mechanism of the Sb2Te3 Phase-Change Thin Film by Inserting Sn15Sb85 Layers.

As a non-volatile semiconductor memory technology, phase-change memory has a wide range of application prospects as a result of the excellent comprehensive performance. In this paper, multilayer thin films based on Sb2Te3 material were designed and prepared by inserting the Sn15Sb85 layer. The thermal and electrical properties of superlattice-like Sb2Te3/Sn15Sb85 phase-change films can be adjusted by controlling the thickness ratio of Sb2Te3/Sn15Sb85. In comparison to the monolayer Sb2Te3 film, the multilayer layer Sb2Te3/Sn15Sb85 materials have a higher crystallization temperature, larger crystallization activation energy, and longer data lifetime, indicating the great improvement of thermal stability. The changes in the phase structure and vibrational modes of multilayer Sb2Te3/Sn15Sb85 films were characterized by X-ray diffraction and Raman spectroscopy, respectively. The presence of Sn15Sb85 layers restrains grain growth and refines the grain size. The multilayer Sb2Te3/Sn15Sb85 films exhibit better surface flatness, smaller surface potential undulation, and lower thickness variations than single-layer Sb2Te3. Phase-change memory cells based on the [Sb2Te3 (1 nm)/Sn15Sb85 (9 nm)]5 thin film has a lower threshold voltage (1.9 V) and threshold current (3.1 μA) compared to the Ge2Sb2Te5 film. Meanwhile, the electrical heating model of a phase-change memory cell based on a [Sb2Te3 (1 nm)/Sn15Sb85 (9 nm)]5 multilayer structure was established by multiphysics coupling analysis, proving the great improvement in heat transfer performance and efficiency. The experimental and theoretical studies confirm that the insertion of the Sn15Sb85 layer can significantly improve the crystallization properties of Sb2Te3 films, paving the way for optimizing the phase-change materials by regulating the microstructural parameters.

Simulation of Gallium Nitride/Aluminum Nitride-Based Triple Barrier Quantum Region for ULTRARAM Application

ULTRARAM is a low-power, high-speed, nonvolatile compound semiconductor memory device that uses triple barrier resonance tunneling (TBRT) to store electrical charge in a floating gate. Using a self-consistent solution of Schrödinger-Poisson equations, we investigated the electrical properties, transmission spectra, and electron dynamics across GaN/AlN TBRT region for the ULTRARAM application. The simulation results show that GaN/AlN exhibits tunable electrical properties by using a TBRT region of variable thickness. Successive optimization and testing of various thicknesses significantly altered the transmission across multiple barriers and localization of electrons in the quantum wells. The program/erase (P/E) operation of GaN/AlN-based ULTRARAM in a triple barrier structure is accomplished at less than 2 V. The device’s excellent nonvolatility is due to the conduction band offset (CBO) of GaN/AlN heterostructure providing a large energy barrier (2.1 eV), which prevents electrons from escaping from the floating gate. Because of the low voltage operation and small capacitance, the switching energy consumption is much lower than that of a standard floating gate Flash.

Microstructure research for ferroelectric origin in the strained Hf0.5Zr0.5O2 thin film via geometric phase analysis

Recently, non-volatile semiconductor memory devices using a ferroelectric Hf0.5Zr0.5O2 film have been attracting extensive attention. However, at the nano-scale, the phase structure remains unclear in a thin Hf0.5Zr0.5O2 film, which stands in the way of the sustained development of ferroelectric memory nano-devices. Here, a series of electron microscopy evidences have illustrated that the interfacial strain played a key role in inducing the orthorhombic phase and the distorted tetragonal phase, which was the origin of the ferroelectricity in the Hf0.5Zr0.5O2 film. Our results provide insight into understanding the association between ferroelectric performances and microstructures of Hf0.5Zr0.5O2-based systems.

Thermionic Emission Based Resistive Memory with Ultrathin Ferroelectric BiFe1–xCrxO3 Films Deposited by Mineralizer-Free Microwave-Assisted Hydrothermal Synthesis

We develop resistive switching memory devices employing ultrathin (∼2.5 nm) BiFe1–xCrxO3 ferroelectric films, deposited by microwave-assisted hydrothermal (MWHT) synthesis, as the potential barrier. BiFeO3 is a multiferroic material highly suitable for nonvolatile semiconductor memories due to its polar and magnetic ordering at room temperature. Chromium is incorporated to enhance the material’s multiferroic properties. As compared to more commonly used physical and chemical vapor deposition tools, MWHT is an extremely cost-efficient tool that provides high reproducibility and stoichiometry control. Using no mineralizer and thereby reducing leakage currents and structural disorder, the ferroelectric phase is reached in our films after 2 cycles of microwave irradiation, and atomic step-terraces can be seen on the surface, attesting to a highly ordered film growth. Using platinum (Pt) top electrodes and conductive substrates (Nb:SrTiO3 and Pt) as bottom electrodes, memory devices are fabricated. Resistive s...

Potentiality of Semiconductor Nonvolatile Memory as the Storage Device for Long-term Preservation of Digital Images -Its Current Status and Issues-

Potentiality of Semiconductor Nonvolatile Memory as the Storage Device for Long-term Preservation of Digital Images -Its Current Status and Issues-

半導体メモリの変遷と今後の展望

半導体メモリの変遷と今後の展望

Unipolar resistive switching in metal oxide/organic semiconductor non-volatile memories as a critical phenomenon

Diodes incorporating a bilayer of an organic semiconductor and a wide bandgap metal oxide can show unipolar, non-volatile memory behavior after electroforming. The prolonged bias voltage stress induces defects in the metal oxide with an areal density exceeding 1017 m−2. We explain the electrical bistability by the coexistence of two thermodynamically stable phases at the interface between an organic semiconductor and metal oxide. One phase contains mainly ionized defects and has a low work function, while the other phase has mainly neutral defects and a high work function. In the diodes, domains of the phase with a low work function constitute current filaments. The phase composition and critical temperature are derived from a 2D Ising model as a function of chemical potential. The model predicts filamentary conduction exhibiting a negative differential resistance and nonvolatile memory behavior. The model is expected to be generally applicable to any bilayer system that shows unipolar resistive switching.

Enhanced non-volatile memory characteristics with quattro-layer graphene nanoplatelets vs. 2.85-nm Si nanoparticles with asymmetric Al2O 3/HfO 2 tunnel oxide.

In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al2O3/HfO2 tunnel oxide and we compare it to the same memory structure with 2.85-nm Si nanoparticles charge trapping layer. The results show that graphene nanoplatelets with Al2O3/HfO2 tunnel oxide allow for larger memory windows at the same operating voltages, enhanced retention, and endurance characteristics. The measurements are further confirmed by plotting the energy band diagram of the structures, calculating the quantum tunneling probabilities, and analyzing the charge transport mechanism. Also, the required program time of the memory with ultra-thin asymmetric Al2O3/HfO2 tunnel oxide with graphene nanoplatelets storage layer is calculated under Fowler-Nordheim tunneling regime and found to be 4.1 ns making it the fastest fully programmed MOS memory due to the observed pure electrons storage in the graphene nanoplatelets. With Si nanoparticles, however, the program time is larger due to the mixed charge storage. The results confirm that band-engineering of both tunnel oxide and charge trapping layer is required to enhance the current non-volatile memory characteristics.Electronic supplementary materialThe online version of this article (doi:10.1186/s11671-015-0957-5) contains supplementary material, which is available to authorized users.

Ferroelectricity and antiferroelectricity of doped thin HfO2-based films.

The recent progress in ferroelectricity and antiferroelectricity in HfO2-based thin films is reported. Most ferroelectric thin film research focuses on perovskite structure materials, such as Pb(Zr,Ti)O3, BaTiO3, and SrBi2Ta2O9, which are considered to be feasible candidate materials for non-volatile semiconductor memory devices. However, these conventional ferroelectrics suffer from various problems including poor Si-compatibility, environmental issues related to Pb, large physical thickness, low resistance to hydrogen, and small bandgap. In 2011, ferroelectricity in Si-doped HfO2 thin films was first reported. Various dopants, such as Si, Zr, Al, Y, Gd, Sr, and La can induce ferro-electricity or antiferroelectricity in thin HfO2 films. They have large remanent polarization of up to 45 μC cm(-2), and their coercive field (≈1-2 MV cm(-1)) is larger than conventional ferroelectric films by approximately one order of magnitude. Furthermore, they can be extremely thin (<10 nm) and have a large bandgap (>5 eV). These differences are believed to overcome the barriers of conventional ferroelectrics in memory applications, including ferroelectric field-effect-transistors and three-dimensional capacitors. Moreover, the coupling of electric and thermal properties of the antiferroelectric thin films is expected to be useful for various applications, including energy harvesting/storage, solid-state-cooling, and infrared sensors.

Design Technology of Stacked‐Type Chain PRAM

SUMMARYA stacked‐type chain PRAM that can result in lower cost than flash memory has been proposed. The newly proposed memory cell uses a PCM for data storage and an MOS transistor connected in parallel. This memory cell is connected in series to realize the chain structure. The cell structure, the design method for realizing stable read and write operation, and the core circuit for the stacked‐type chain PRAM are described. The newly proposed memory cell has been designed to use BiCS (Bit Cost Scalable) process technology in order to achieve low‐cost memory. The design of the resistance of the PCM and the pass transistor is a key issue for realizing stable operation. To design the row decoder, the circuit concept of stacked ferroelectric RAM (FeRAM) with an NAND structure cell has been successfully adopted with SGT. The newly proposed stacked‐type chain PRAM is a promising candidate for realizing high‐speed and low‐power future nonvolatile semiconductor memory.

Reactive magnetron sputtered hafnium oxide layers for nonvolatile semiconductor memory devices

The feasibility of the application of double-gate dielectric stacks with fabricated by r.f. reactive magnetron sputtering hafnium oxide layers in nonvolatile semiconductor memory (NVSM) devices was investigated. Significant retention time was demonstrated. A very broad memory window (extrapolated at 10 years) of flat-band voltage (UFB) value of the order of 2.6 V was obtained. Moreover, the stability of the electrical characteristics of metal–insulator–semiconductor structures after gamma and electron irradiation have been observed, which proved that the investigated double-gate dielectric stacks are promising for future applications in NVSM radiation-hard devices.

Electroforming-Free and Multilevel Resistance Switching Properties in Al/TiOx/Cu Structure

Resistance random access memory (RRAM) in various oxide materials,especiallybinaryoxidematerialssuchasTiO2, 1 ZrO2, 2 HfO2, 3 and ZnO, 4 has attracted considerable attention as one of the promising applications in next-generation nonvolatile semiconductor memory devices. Although the resistance switching (RS) materials can be classified into several groups according to switching mechanisms, this study focuses on combined different mechanisms effects on the RS performance in Al/TiOx/Cu. As Cu is an active metal in the electrochemical metallization memory (ECM), 5 adopting Cu as electrode may induce Cu conductive filaments (CFs). Meanwhile, because of the higher oxidation potential of Al compared with Ti, 6 adopting Al onTiOx mayinducetheoxygenvacancy (Vo)relatedRSmechanisms, such as electronic switching related with the trapping and detrapping of carriers along the Vo channels. 7 Particularly, when RRAM devices is programmed, a filament with trap-controlled space charge limited current (SCLC) could be formed, while a metallic CFs could also be formed. Therefore, multilevel resistance states may be obtained by forming different filaments inside the device. However, research on combining these two mechanisms remains to be clarified. During the resistance switching process, the “electroforming” process is usually needed to obtain the resistance switching. However, this process often results in the random fluctuations of switching parameters and needs a much higher bias, which are generally unfavorable for the device fabrication and operation. 8 In this paper, the characteristics of multilevel resistance switching, electroforming-free and low Ireset (the maximum current level changes from LRS to HRS) were investigated through Al/TiOx/Cu structure. The relationship between electroforming-free and low Ireset will be elucidated in this paper, as well as the multilevel resistance switching mechanism.

Effects of Composition on the Memory Characteristics of (HfO2)x(Al2O3)1-xBased Charge Trap Nonvolatile Memory

According to the 2012 International Technology Roadmap for Semiconductors (ITRS) [1], the conventional floating gate nonvolatile semiconductor memories (FG-NVSM) are approaching their scaling limitation; moreover, new materials and technology are required in order to explore the novel solid state nonvolatile memory device with the desired characteristics, such as the low-cost, high-density and a fast program/erase (P/E) speed for use in mobile electronics [2-5]. For conventional FG-NVSM devices, the charges are stored in a conducting poly-silicon gate, and a single defect in the tunneling layer can discharge the whole memory due to the scaling thickness of the tunneling layer. Based on the concept, that charges are stored in discrete traps within the charge trapping layer, silicon-oxide-nitrideoxide-silicon (SONOS) charge trap flash (CTF) memories with nitride (Si3N4), as the charge trapping layer, have attracted much attention for commercial applications in order to replace the conventional FG-NVSM devices due to lower operating voltage, excellent endurance, smaller size and compatibility with standard CMOS technology [6]. However, one problem in the SONOS memory device is the small conduction band offset between the Si3N4 and the tunneling layer [7], which leads to poor retention characteristics. In order to solve the problem, employing high-k dielectrics, as the charge trapping layer in the SONOS structure, has been reported by many researchers [8-14]. The charge memory structure with a pure HfO2 charge trapping layer demonCharge trap flash memory capacitors incorporating (HfO2)x(Al2O3)1-x film, as the charge trapping layer, were fabricated. The effects of the charge trapping layer composition on the memory characteristics were investigated. It is found that the memory window and charge retention performance can be improved by adding Al atoms into pure HfO2; further, the memory capacitor with a (HfO2)0.9(Al2O3)0.1 charge trapping layer exhibits optimized memory characteristics even at high temperatures. The results should be attributed to the large band offsets and minimum trap energy levels. Therefore, the (HfO2)0.9(Al2O3)0.1 charge trapping layer may be useful in future nonvolatile flash memory device application.

Characteristics of phase transition in boron‐implanted Ge2Sb2Te5 thin films for phase change memory applications

Phase change memory has been considered as one of the most promising alternatives for next‐generation nonvolatile semiconductor memory. Modification of phase change materials by impurity doping has been proved to be an effective way to improve phase change memory device performance. In this study, the most common phase change material, Ge2Sb2Te5 (GST), was employed, and its intrinsic properties were modified using boron–ion implantation. The GST films were implanted with 20 keV boron ions to fluences of 5 × 1014 and 5 × 1015 ions/cm2. The characteristics of the virgin and boron‐implanted GST films were investigated by SIMS, XRD, and in situ resistance measurement. The kinetics of the thermally activated phase transition was also analyzed on the basis of the Arrhenius relationship. The results revealed that both crystallization temperature and activation energy of crystallization increase with increasing the boron fluence. The data retention capability is also enhanced from 83 to 88 °C, corresponding to a criterion of 10‐year archival lifetime. In addition, the XRD spectra indicated that high‐fluence boron–ion implantation partially inhibits the transition of the GST films from face‐centered cubic phase to hexagonal close‐packed phase. In conclusion, the thermal stability of the GST films can be improved through boron–ion implantation. Copyright © 2014 John Wiley &amp; Sons, Ltd.

Carrier mobility determination with a two-terminal ‘gridded’ capacitor

We present a method to calculate the carrier mobility in MOSFET’s and charge trap, nonvolatile semiconductor memories (NVSMs) with a two terminal structure. The method employs a ‘gridded’ capacitor to supply minority carriers, thereby, alleviating the need to fabricate a transistor with source/drain contacts. Capacitance and conductance measurements are employed to extract carrier mobility. Although this approach is applied to silicon, the method is versatile and can be employed on other materials.

Resistive Switching Effect in Titanium Oxides

Resistive switching (RS) phenomena have been vigorously investigated in a large variety of materials and highlighted for its preeminent potential for the future nonvolatile semiconductor memory applications or reconfigurable logic circuits. Among the various resistive switching materials, the binary metal oxides demonstrate more advantageous for micro- or nano-electronics applications due to their simpler fabrication process and compatibility with conventional CMOS technology, though the mechanisms are controversial due to the diversity of RS effects. This review mainly focuses on the current understanding of the microscopic nature of RS in titanium oxides, in which the working mechanisms can be categorized into thermochemical metallization mechanism, valence change mechanism, and electrostatic/electronic mechanism. The approaches developed to investigate the RS and the specific switching processes related to different mechanisms are addressed. Since titanium oxides are oxygen-vacancy doped semiconductors, the role of defects is analyzed in detail and possible effective strategies to improve the performance of RS are addressed.

Double gate dielectric stacks with Gd2O3 layer for application in NVSM devices

This work presents the feasibility study of application of gadolinium trioxide (Gd2O3) layers in double-gate dielectrics stacks for non-volatile semiconductor memories (NVSM). In the course of this work metal–insulator–semiconductors (MIS) structures with SiO2/Gd2O3 stacks have been fabricated and characterised by means of current–voltage (I–V) and split-CV techniques. Moreover, memory characteristics were investigated and compared to MIS structures with stacks based on atomic layer deposited (ALD) hafnium dioxide (HfO2) and aluminum trioxide (Al2O3) layers. Presented results have shown low leakage current density of fabricated SiO2/Gd2O3 of the order of 10−6A/cm2 at 5MV/cm of equivalent electric field intensity, low interface trap density (Nit) ∼2×1011cm−2 and moderate mobility of MISFETs with studied stacks in the range of 140–380cm2V−1s−1. Moreover, the decrease of retention time extrapolated at ten years of the order of 12% was determined which is significantly lower in comparison to MIS stacks with ALD high-k dielectric layers. In the case of MISFET’s threshold voltage (Ut) relatively broad memory window has been obtained around 1.67V which makes the investigated double-gate dielectric stack as the potential candidate for low voltage memory applications.

(Invited) Storage Class Memory and NAND Flash Memory Hybrid Solid-State Drives (SSD)

SSDs and emerging storage class non-volatile semiconductor memories (SCM) such as PCRAM, FeRAM, ReRAM and MRAM have enabled innovations in various nano-scale VLSI memory systems for personal computers, multimedia applications and enterprise servers. This paper provides a comprehensive review on state-ofthe-art data management technologies of storage class memory and NAND flash memory hybrid solid-state drives (SSDs)

Analog memristive memory with applications in audio signal processing

Since the development of the HP memristor, much attention has been paid to studies of memristive devices and applications, particularly memristor-based nonvolatile semiconductor memory. Owing to its unique properties, theoretically, one could restart a memristor-based computer immediately without the need for reloading the data. Further, current memories are mainly binary and can store only ones and zeros, whereas memristors have multilevel states, which means a single memristor unit can replace many binary transistors and realize higher-density memory. It is believed that memristors can also implement analog storage besides binary and multilevel information memory. In this paper, an implementation scheme for analog memristive memory is considered. A charge-controlled memristor model is derived and the corresponding SPICE model is constructed. Special write and read operations are demonstrated through numerical analysis and circuit simulations. In addition, an audio analog record/play system using a memristor crossbar array is designed. This system can provide great storage capacity (long recording time) and high audio quality with a simple small circuit structure. A series of computer simulations and analyses verify the effectiveness of the proposed scheme.

Modern flash technologies: a flash translation layer perspective

Since the introduction of the first flash memory in 1984, flash memory has been a very important member of the non-volatile semiconductor memory family due to its advantages, such as high density, low-cost, shock resistance, fast access time, low-power consumption and reliability. Despite the advantages, flash memory is still facing many technical limitations that need to be further studied. Various solutions have been developed to improve the performance of flash memory by overcoming the technical limitations; however, flash translation layer has a great impact on the overall performance improvement due to its cost-efficiency and usefulness. In this paper, three main aspects of flash memory are discussed from a perspective of flash translation layer. First, we discuss and classify flash translation layer based on the mapping method. Second, we discuss the current technical limitations that flash memory is facing and how these can be overcome by adopting flash translation layer. Third, we investigate the latest flash translation layer schemes that have been recently studied and proposed, and analyse their advantages and drawbacks.