Enhanced non-volatile memory characteristics with quattro-layer graphene nanoplatelets vs. 2.85-nm Si nanoparticles with asymmetric Al2O 3/HfO 2 tunnel oxide.

Nazek El-Atab,Berk Berkan Turgut,Ammar Nayfeh,Munir Nayfeh,Ali K Okyay

doi:10.1186/s11671-015-0957-5

Abstract

In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al2O3/HfO2 tunnel oxide and we compare it to the same memory structure with 2.85-nm Si nanoparticles charge trapping layer. The results show that graphene nanoplatelets with Al2O3/HfO2 tunnel oxide allow for larger memory windows at the same operating voltages, enhanced retention, and endurance characteristics. The measurements are further confirmed by plotting the energy band diagram of the structures, calculating the quantum tunneling probabilities, and analyzing the charge transport mechanism. Also, the required program time of the memory with ultra-thin asymmetric Al2O3/HfO2 tunnel oxide with graphene nanoplatelets storage layer is calculated under Fowler-Nordheim tunneling regime and found to be 4.1 ns making it the fastest fully programmed MOS memory due to the observed pure electrons storage in the graphene nanoplatelets. With Si nanoparticles, however, the program time is larger due to the mixed charge storage. The results confirm that band-engineering of both tunnel oxide and charge trapping layer is required to enhance the current non-volatile memory characteristics.Electronic supplementary materialThe online version of this article (doi:10.1186/s11671-015-0957-5) contains supplementary material, which is available to authorized users.

Highlights

The demand for low-power, high-speed, and highdensity non-volatile memory devices has increased drastically over the past decade due to the growing market of consumer electronics
In addition to the trade-off relationship between tunnel oxide thickness and retention characteristic of the memory where the retention of charges is exponentially degraded as the tunnel oxide thickness is scaled down, there exists another trade-off relationship between the tunnel oxide thickness and the resulting program time, where a thicker tunnel oxide causes the extension of the time needed for the charges to be transported from the channel to the charge trapping layer and vice-versa
A 4-nm Al2O3 tunnel oxide is first deposited by thermal atomic layer deposition (ALD) at 250 °C using a Cambridge Nanotech Savannah-100 atomic layer deposition system followed by 1.1 nm HfO2 deposited by plasma-assisted ALD (PA-ALD) at 195 °C using an Oxford FlexAL system

Summary

Introduction

The demand for low-power, high-speed, and highdensity non-volatile memory devices has increased drastically over the past decade due to the growing market of consumer electronics. The density of the memory is related to the gate length scaling which is constrained by the gate stack, precisely, the tunnel oxide thickness. In conventional flash memories, the tunnel oxide thickness has a lower limit of 6–8 nm (depending on NOR or NAND structure) in order to avoid back-tunneling and leakage of charges which destroys the necessary retention characteristic of the memory (>10 years). The second problem which needs to be solved is the high program and erase operating voltages. The limitation to operating voltage scaling is the inability to reduce gate stack thickness. It is imperative to find novel structures and materials to be incorporated in

Methods

Results

Conclusion