5 - Laser ablated nanoparticles synthesis

Abstract

High density, low power consumption, and low cost memory cells are exceedingly desired due to the continuous scaling of the memory cells and the augmentation in memory array dimensions. The program/erase (P/E) speed of the floating-gate memory can be enhanced by reducing the thickness of the tunnel oxide to sub 2.5 nm, which would result in 100 ns P/E time at a tolerable programming voltage (<10 V). However, the retention time would be significantly degraded and the stress-induced leakage current (SILC) would further worsen it, resulting in an unreliable device. Due to this challenge, current commercial memory devices have thick tunnel oxides (∼8 nm) to guarantee the 10 year data retention, subsequently high operating voltages with slow speeds are obtained. The deployment of nanoparticles as the charge trapping layer has been proposed as a solution. In fact, unlike the floating gate memory device, which is totally discharged once a single defect is present in the tunnel oxide, nanoparticles based memories discharge only the stored charge in the nanoparticle existing above the tunnel oxide defect. This enables the use of thinner tunnel oxides, and subsequently, lower P/E voltages and larger speeds can be attained without compromising the good retention characteristic (>10 years). In this chapter, we study the effect of embedding 2-nm Si nanoparticles in the charge trapping layer on the memory device behavior. Two memory structures are studied with a ZnO channel and different charge trapping layers: Si nanoparticles only and Si nanoparticles embedded in a ZnO layer.