Nonthreshold Logic Research Articles

Modeling for bridging faults in nMOS combinational circuits

A transistor level model that fully describes the logical behavior of a circuit in the presence of bridging faults is presented for the nMOS combinational circuits. The proposed model is suitable for the circuits having static enhancement/depletion (E/D) load. Thus, the model can be applied to circuits like pseudo nMOS and CMOS non-threshold-logic (NTL). The model employs a logic transistor function (LTF) to examine the behavior of such circuits. The LTF model developed earlier for stuck faults in nMOS circuits is extended for bridging faults. Algorithms that were developed for the stuck faults in pseudo nMOS combinational circuits can be applied to generate the test vectors for bridging faults.

Active-pull-down nonthreshold logic BiCMOS circuits for high-speed low-power applications

A new active-pull-down nonthreshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate. The circuit utilizes an NMOS active-pull-down emitter-follower stage. A first-order analysis has been conducted to demonstrate the NMOS-APD concept. Simulation results based on 0.6 /spl mu/m BiCMOS technology indicate that at a power consumption of 1 mW/gate, the APD-NTL circuit offers 4/spl times/ improvement in the load driving capability and 3.4/spl times/ improvement in the speed compared to conventional NTL circuits for a load of 1 pF/gate and a logic swing of 800 mV.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modeling for stuck faults in cmos non-threshold logic (NTL) combinational circuits

In this paper, a transistor model is presented for CMOS Non Threshold Logic (NTL) combinational circuits. This model employs the logic transistor function (LTF) to examine the behavior of CMOS Non Threshold Logic (NTL) circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault free LTF by using a systematic procedure. The model assumes the logic values 0, 1, I , M, where, I and M imply an intermediate logical value and a memory element, respectively. Both classical stuck-at faults and non classical transistor stuck faults can be analyzed by this model. Primitive D-cubes of the fault can be extracted for a specified subcircuit. To generate test for single or multiple faults, a variant of the D-algorithm may be used. Algorithms that were developed for Pseudo NMOS combinational circuits can be directly applied to generate test vectors.

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors

While an ECL-CMOS SRAM can achieve both ultra high speed and high density, it consumes a lot of power and cannot be applied to low power supply voltage applications. This paper describes an NTL (Non Threshold Logic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS memory cell, an NTL decoder with an on-chip voltage generator, and an automatic bit line signal voltage swing controller. A 32 Kb SRAM macro, which achieves a 1 ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 /spl mu/m BiCMOS technology.

Non-quasi-static effects in advanced high-speed bipolar circuits

A detailed study on the non-quasi-state (NQS) effects in advanced high-speed bipolar circuits is presented. An NQS Gummel-Poon-compatible lumped circuit model, which accounts for carrier propagation delays across various quasi-neutral regions in bipolar devices, is implemented in the ASTAP circuit simulator. The effects are then evaluated and compared with those for the conventional Gummel-Poon model for the emitter-coupled logic (ECL) circuit, the non-threshold-logic (NTL) circuit, and various advanced circuits utilizing active-pull-down schemes. For the ECL circuit, the effect decreases with reduced power level and increased loading. For the NTL circuit, due to its front-end configuration, the effect is more significant than that for the ECL circuit but tends to increase with reduced power level. As the passive resistors (and the associated parasitic RC effect) are decoupled from the delay path and the circuit delay is made more intimately related to the intrinsic speed of the devices in various advanced active-pull-down circuits, the delay degradation due to NQS effect becomes more significant. >

73-GHz self-aligned SiGe-base bipolar transistors with phosphorus-doped polysilicon emitters

The authors report a thermal-cycle emitter process using phosphorus for the fabrication of self-aligned SiGe-base heterojunction bipolar transistors. The low thermal cycle results in extremely, narrow basewidths and preservation of lightly doped spacers in both the emitter-base and base-collector junctions for improved breakdown. Transistors with 35-nm basewidths were obtained with low emitter-base reverse leakage and a peak cutoff frequency of 73 GHz for an intrinsic base sheet resistance of 16 k Omega / Square Operator . Minimum NTL (nonthreshold logic) and ECL (emitter-coupled logic) gate delays of 28 and 34 ps, respectively were obtained with these devices. >

On the leverage of high-f/sub T/ transistors for advanced high-speed bipolar circuits

A detailed study on the leverage of high-f/sub T/ transistors for advanced high-speed bipolar circuit applications is presented. It is shown that for the standard ECL (emitter-coupled logic) circuit, the leverage of high f/sub T/ is limited by the passive resistors (emitter-follower resistor and collector load resistor) and wire delay, especially in the low-power regime. For the standard NTL (nonthreshold logic) circuit, the leverage is higher due to its front-end configuration and lower power supply value. As the passive resistors are decoupled from the delay path in various advanced circuits utilizing active-pull-down schemes, the leverage of high F/sub T/ becomes more significant. >

NTL with complementary emitter-follower driver: a high-speed low-power push-pull logic circuit

A high-speed low-power nonthreshold-logic (NTL)-based push-pull logic circuit, featuring a complementary emitter-follower driver is presented. Compared with the standard NTL circuit, the circuit offers a much better balance between the pull-up and pull-down delay, improved scalability, and superior load driving capability. Simulation results based on a 0.8- mu m double-poly. self-aligned complementary bipolar technology indicate that at a power consumption of 1.22 mW/gate, the circuit offers 2.4* improvement in the pull-down delay of a loaded gate and 4.0* improvement in the load driving capability over the standard NTL circuit. The design and scaling considerations of the circuit are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New physical timing models of bipolar nonsaturation logic using current-domain analysis technique

A new large-signal equivalent circuit with input and output current signals for a nonsaturated bipolar junction transistor has been developed. Based upon this equivalent circuit, physical timing models of direct-coupled transistor logic (DCTL) and nonthreshold logic (NTL) have been derived through a general modeling methodology. It is shown from extensive comparisons with SPICE simulation results that the models have a maximum error of 25% in single-stage delay calculation and 10% in multi-stage delay calculation. Experimental results on NTL ring oscillators also partly substantiate the developed current-domain large-signal equivalent circuit and physical timing models. Good accuracy, wide applicable ranges of device/circuit parameters and input waveforms, and less CPU time and memory consumption than full transient simulations make the physical timing models feasible in optimization and CAD of high-speed bipolar ICs.

BiCMOS nonthreshold logic for high-speed low-power applications

New high-speed low-power BiCMOS nonthreshold logic (BNTL) circuits are presented. These circuits offers a built-in CMOS and bipolar level conversion and are suitable for reduced power supply voltage. A 4-b carry lookahead generator (CLG) circuit is designed in BNTL, ECL, and CMOS using 0.8- mu m BiCMOS technology. Circuit simulations show that this new logic provides speed comparable to or better than that provided by emitter-coupled logic (ECL) for lower power dissipation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Physical timing models and design methodology of bipolar nonthreshold logic circuits

Physical timing models have been derived by using the current-domain BJT equivalent circuit for high-speed low-power bipolar NTL circuits. The design methodology of the shunt capacitance C E and the emitter length of bipolar NTL circuits has also been developed in this study. It is shown that the optimal value of the shunt capacitance C E is equal to 1–1.25 C E0 where C E0 is the shunt capacitance of NTL circuit without voltage or current overshooting and undershooting. Both an exact model and a simplified model for C E0 have been derived. Applying the developed timing models and design methodology, the sizing of NTL gates and taper buffers have been successfully performed as application examples.

Performance degradation due to extrinsic base encroachment in advanced narrow-emitter bipolar circuits. I. Basic inverter

It is shown that, depending on the circuit families used, the extrinsic base encroachment results in distinct effects on the operation and performance of the circuits. The design considerations and scaling implications, using a basic inverter as an example for a saturating circuit, are discussed. It is shown that while the extrinsic base encroachment causes increases in the delay time, fall time, and risetime of a basic bipolar junction transistor inverter, the saturation time of the inverter actually decreases, since the transistor is driven less deeply into saturation due to reduced collector current (reduced current gain). The decrease in the saturation time, however, is accompanied by the reduced noise margin, especially for narrow emitter stripes. Cases for nonsaturating circuits are discussed in Part II using nonthreshold logic as an example. >

Performance degradation due to extrinsic base encroachment in advanced narrow-emitter bipolar circuits. II. Non-threshold logic circuits

For pt.I see ibid., vol.36, no.9, p.1751-6 (1989). In the steady state, the extrinsic base encroachment is shown to force the current to flow through the center of the emitter, resulting in higher current density and more severe base stretching at the center of the emitter. During the switching transient, the current flows predominantly through the emitter edge, and the turn-on delay is governed mainly by the perimeter thick base at the emitter edge. The extrinsic base encroachment also limits the overdrive (and hence the speed) of the nonthreshold logic circuit when a speed-up capacitor is used. The base stretching at the center of the emitter is shown to be enhanced by the speed-up capacitor. Because of the modification of the emitter Gummel number near the emitter edge by the extrinsic base encroachment and the transient edge conduction mechanism, significantly more holes are injected into the emitter during the switching transient than in the steady state. This back injection is shown to be further enhanced by the speed-up capacitor. The design considerations for scaled-down devices are discussed. >

High performance InP/InGaAs heterostructure bipolar transistors grown by metalorganic vapor phase epitaxy

We demonstrate high performance InGaAs/InP heterostructure bipolar transistors grown by metalorganic vapor phase epitaxy. A unity current gain cutoff frequency fT=78 GHz and a maximum oscillation frequency fmax=42 GHz are achieved in transistors with emitter size 2.5×11 μm2. Ring oscillators using nonthreshold logic show a propagation delay of 31 ps.

A 20-ps Si bipolar IC using advanced super self-aligned process technology with collector ion implantation

A super self-aligned process technology, SST-1B, which is an advanced version of the previously proposed SST-1A in high-speed Si bipolar LSIs is discussed. A selectively ion-implanted collector (SIC) process and bird's-beak-free isolation process are utilized. The SIC process is designed to improve shallow base-collector profiles in the intrinsic region. It reduces base width and intrinsic base resistance, and suppresses the base push-out effect (Kirk's effect) in high-current operations. The SIC profile is easily controlled by 150-200 keV phosphorous ion implantation at the base-collector junction. Using these processes, SST-1B has achieved a high cutoff frequency of 21.1 to 25.7 GHz and a fast switching delay of 20.5 ps/G for nonthreshold logic and 34.1 ps/G for emitter-coupled logic. SST-1B has potential applications to 50-ps/G logic LSIs and 10-GHz SSIs. Device simulation indicates that it is possible to achieve a cutoff frequency of 40-50 GHz in a future scaled-down Si bipolar transistor with a 40-nm base and graded collector. >

CMOS nonthreshold logic (NTL) and cascode nonthreshold logic (CNTL) for high-speed applications

The CMOS nonthreshold logic (NTL) is derived from its bipolar counterpart, which is the fastest bipolar logic, and takes the NOR gate as its basic building gate. It is shown that by applying the nonthreshold principle to CMOS circuits speed performance can be highly improved, but with an increase of DC power consumption. From transient analyses the speed of CMOS NTL is found quite comparable to that of I/sup 2/L (integrated injection logic) or even ECL (emitter-coupled logic) and is about 20-60% better than that of conventional CMOS. Meanwhile, the power-delay product of CMOS NTL is smaller than those of I/sup 2/L and ECL and is nearly the same as that of conventional CMOS operated at high frequency. The nonthreshold principle is applied to the CMOS cascode structure to form the CMOS cascode nonthreshold logic (CNTL), in which there is a tradeoff between speed performance and power dissipation. It is shown from the design of full adders that the CMOS NTL is the fastest of all the static CMOS logic circuits. The speed of the CNTL circuit, although slower than that of the NTL circuit, is still higher than that of the DSL circuit, which is the fastest static circuit proposed so far. The CNTL circuit also has a smaller power-delay product than the DSL circuit. >

Subpicosecond InP/InGaAs heterostructure bipolar transistors

Bipolar transistors with subpicosecond extrinsic delay are discussed. These InP/InGaAs heterostructure transistors show a unity-current-gain cutoff frequency f/sub $/T=165 GHz and maximum oscillation frequency f/sub MAX/=100 GHz at room temperature. The authors model shows that an f/sub $/T beyond 386 GHz is obtainable by further vertical scaling. Ring oscillators implemented with nonthreshold logic (NTL) and transistors having f/sub MAX/=71 GHz show a propagation delay of 14.7 ps and 5.4 mW average power consumption per stage. >

Self-aligned AlInAs/GainAs HBTs for digital IC applications

An AlInAs/GaInAs HBT with a self-aligned device structure has been realised. The smallest device has an emitter-base junction area as small as 1.0×10 μm. A 17-stage nonthreshold logic (NTL) ring oscillator is also fabricated, which is the first logic IC implemented with HBTs on InP substrates.

A 50-ps 7 K-gate masterslice using mixed cells consisting of an NTL gate and an LCML macrocell

A 7 K-gate bipolar masterslice providing high-speed gates as well as highly functional cells has been developed. A basic mixed cell consisting of both a nonthreshold logic (NTL) gate and an LCML macrocell is introduced. A 1-/spl mu/m-rule super self-aligned process technology (SST-1A) is adopted in combination with three-level metallization technology. A basic NTL gate delay of 50 ps has been achieved with a power dissipation of 1.84 mW. For flip-flop (FF) performance using a macrocell, a toggle frequency of up to 2.6 GHz is obtained with 3.78 mW/FF. For application, a 24-bit parallel multiplier having a multiplication time of 12.8 ns is customized with a power dissipation of 5.1 W.

A 30-ps Si bipolar IC using super self-aligned process technology

A new 30-ps Si bipolar IC technology has been developed by scaling down a bipolar transistor's lateral geometry and forming shallow junctions. The n-p-n transistor has a 0.35-µm-wide emitter and a 1.57-µm-wide base region fabricated using super self-aligned process technology (SST) with 1-µm rule optical lithography. The f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> values achieved for this device are 13.7 GHz at a collector-emitter voltage of 1 V and 17.1 GHz at 3 V. Propagation delay times (fan-in = fan-out = 1) of 30 ps/gate at 1.48 mW/gate for nonthreshold logic and 50 ps/ gate at 1.46 mW/gate for low-level current mode logic have been achieved.