Physical timing models and design methodology of bipolar nonthreshold logic circuits

Abstract

Physical timing models have been derived by using the current-domain BJT equivalent circuit for high-speed low-power bipolar NTL circuits. The design methodology of the shunt capacitance C E and the emitter length of bipolar NTL circuits has also been developed in this study. It is shown that the optimal value of the shunt capacitance C E is equal to 1–1.25 C E0 where C E0 is the shunt capacitance of NTL circuit without voltage or current overshooting and undershooting. Both an exact model and a simplified model for C E0 have been derived. Applying the developed timing models and design methodology, the sizing of NTL gates and taper buffers have been successfully performed as application examples.