Nominal Gate Length Research Articles

New short-channel n-MOSFET current-voltage model in strong inversion and unified parameter extraction method

A semiempirical strong inversion current-voltage (I-V) model for submicrometer n-channel MOSFETs which is suitable for circuit simulation and rapid process characterization is proposed. The model is based on a more accurate velocity-field relationship in the linear region and finite drain conductance due to the channel length modulation effect in the saturation region. The parameter extraction starts from the experimental determination of the MOSFET saturation current and saturation voltage by differentiating the output characteristics in a unified and unambiguous way. These results are used in order to systematically extract the device and process parameters such as the effective electron saturation velocity and mobility, drain and source series resistances, effective gate length and characteristic length for channel length modulation, and short-channel effects. The values agree well with other independent measurements. The results of experimental studies of wide n-MOSFETs with nominal gate length of 0.8, 1.0, and 1.2 mu m fabricated by an n-well CMOS process are reported. The calculated I-V characteristics using the extracted parameters show excellent agreement with the measurement results.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New continuous heterostructure field-effect-transistor model and unified parameter extraction technique

A continuous model for heterostructure field-effect transistors (HFETs) suitable for circuit simulation and device characterization is proposed. The model is based on the analytical solution of a two-dimensional Poisson equation in the saturation region. The HFET saturation current and saturation voltage have been experimentally determined by differentiating the output characteristics in a unified and unambiguous way. The results are used for the systematic extraction of device and process parameters. The deduced values agree well with other independent measurements. The results of experimental studies of HFETs with nominal gate lengths of 1, 1.4, 2, and 5 mu m are reported. The models and techniques presented here are successfully applied to all these devices. A large short-channel effect is observed for the 1- mu m-gate HFET. The gate length dependences of the device parameters determined by the method reveal that the effective gate length in the self-aligned structures is approximately 0.25 mu m shorter than the nominal gate length.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

InP-based HIGFETs for complementary circuits

Summary form only given. The authors report p-channel heterostructure FETs fabricated on InP substrates, as well as advanced results on submicrometer n-channel HIGFETs. P-HIGFETs with 1- mu m nominal gate lengths were made using lattice-matched InGaAs channels and InAlAs barriers. Threshold voltage and threshold uniformity were studied as a function of gate length for n-channel InGaAs/InAlAs HIGFETs in the range from 0.4 to 1.2 mu m. Microwave characterization of several n-HIGFET wafers with gate lengths down to 0.3 mu m yielded cutoff frequencies of up to 115 GHz, corrected for pad capacitance, with an effective drift velocity of 2.0*10/sup 7/ cm/s. >

A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array

A 0.8- mu m polycide-gate, double-layer-metal CMOS technology is described. Nominal device gate lengths down to 0.8 (+or-0.2) mu m are used for both n- and p-channel transistors. Compact isolation, 175-A gate oxide grown in dry/wet/dry ambient, shallow-junction halo-implanted lightly doped drain n and p devices, TiN contact barrier, and a planarized double-layer-metal process are all integrated and demonstrated with a 0.8- mu m full-CMOS 16K SRAM (static random-access memory) circuit. The device process integrity, design margins, performance, reliability, product yield and speed enhancement are all discussed in detail.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Microwave performance of ion-implanted InP JFETs

These devices have a planar structure with the channel and gate regions formed by the selective implantation of silicon and beryllium into an Fe-doped semi-insulating InP substrate. The nominal gate length is 2 mu m with a channel doping of 10/sup 17/ cm/sup -3/ and thickness of 0.2 mu m. The measured values of f/sub T/ and f/sub max/ are 10 and 23 GHz, respectively. Examination of the equivalent circuit parameters and their variation with bias led to the following conclusions: (a) a relatively gradual channel profile results in lower than desired transconductance, but also lower gate-to-channel capacitance; (b) although for the present devices, the gate length and transconductance are the primary performance-limiting parameters, the gate contact resistance also reduces the power gain significantly; (c) the output resistance appears lower than that of an equivalent GaAs MESFET, and requires a larger V/sub DS/ to reach its maximum value; and (d) a dipole layer forms and decouples the gate from the drain with a strength that falls between that of previously reported GaAs MESFETs and InP MESFETs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Fully implanted p-column InP field-effect transistor

P-column junction field-effect transistors (FET's) have been fabricated in semi-insulating InP utilizing an all-implanted planar technology. A periodic array of p+ columns implanted through an n-type channel layer is used to form the active region. Initial devices with nominal gate lengths of 4 µm exhibit a unity-power-gain frequency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f_{\max}</tex> as high as 7 GHz while recent smaller gate length devices (nominally 1.7µm) show an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f_{\max}</tex> of 16 GHz.

Large grain CdTe thin films on SbBi alloy-coated Ta substrates: Nicola Romeo and Richard H Bube,J Vac Sci Technol, 21 (4), 1982, 969–971

A GaAs MESFET fabrication process based on self-aligned WSi gates with gatelengths down to 0.5 μm is described. A buried p-layer is employed to suppress short-channel effects. The shallow FET channels are connected to the deeper implants of the ohmic source and drain contacts by means of an intermediate-dose “lightly-doped drain” (LDD) implant. Owing to a planarization concept which allows the use of a low-resistance Au overlayer on top of the high resistivity WSi gates, the process yields FETs with excellent high-frequency performance. This is proved by transit frequencies ƒt exceeding 30 GHz, maximum frequencies of oscillation ƒmax of typically 100 GHz, and a noise figure NFmin of 1.0 dB at 12 GHz (nominal gatelength 0.5 μm). FETs with three different threshold voltages are fabricated. All three types of transistors have transconductances of 300 mS/mm or above. This combination of properties makes the technology suitable for the realization of digital as well as microwave circuits.

Modelling ion beam milling: D W Youngner and C M Haynes,J Vac Sci Technol, 21 (2), 1982, 677–680

A GaAs MESFET fabrication process based on self-aligned WSi gates with gatelengths down to 0.5 μm is described. A buried p-layer is employed to suppress short-channel effects. The shallow FET channels are connected to the deeper implants of the ohmic source and drain contacts by means of an intermediate-dose “lightly-doped drain” (LDD) implant. Owing to a planarization concept which allows the use of a low-resistance Au overlayer on top of the high resistivity WSi gates, the process yields FETs with excellent high-frequency performance. This is proved by transit frequencies ƒt exceeding 30 GHz, maximum frequencies of oscillation ƒmax of typically 100 GHz, and a noise figure NFmin of 1.0 dB at 12 GHz (nominal gatelength 0.5 μm). FETs with three different threshold voltages are fabricated. All three types of transistors have transconductances of 300 mS/mm or above. This combination of properties makes the technology suitable for the realization of digital as well as microwave circuits.

High frequency divider circuits using ion-implanted GaAs MESFET's

A single clock master-slave frequency divider circuit was designed and fabricated using GaAs MESFET's in the direct-coupled FET logic (DCFL) circuit architecture. At room temperature, the maximum operating frequency was 6.2 GHz at a power consumption of 3.5 mW/gate. The complete divider circuit and buffer amplifier was realized in a 65 × 165 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area. The MESFET's were fabricated using Si ion implantion directly into GaAs wafers and used a self-aligned recessed gate. The nominal gatelength was 0.6 µm. Corresponding fabricated ring oscillator circuits showed minimum gate delays of 18.5 ps at 3.1 mW/gate for fan-out of one at 300 K and 15.2 ps at 3.5 mW/gate at 77 K.

A 10-GHz frequency divider using selectively doped heterostructure transistors

We report the first complementary clocked frequency divider using dual gate selectively doped heterostructure transistors (SDHT's). The circuit employs a master-slave flip-flop design which consists of four direct coupled AND-NOR gates. The nominal gate length and the gate-gate, separation in the dual gate SDHT's are 1 µm. A maximum dividing frequency of 10.1 GHz at 77 K was achieved; at this frequency the circuit dissipated 49.9 mW at 1.67-V bias. This is the highest operating frequency reported for static frequency dividers at any temperature. At room temperature the dividers were operated successfully at frequencies up to 5.5 GHz with a total power dissipation of 34.8 mW at 1.97-V bias. The lowest speed-power product at room temperature was obtained at 5 GHz with 14.9-mW power dissipation at 1.45-V bias.

The effect of logic cell configuration, gatelength, and fan-out on the propagation delays of GaAs MESFET logic gates

In this work, three different logic cell configurations, two with and one without a source-follower are employed: These logic cells are arranged in 5- and 11-stage ring oscillator (RO) circuits. The circuits are then fabricated with nominal gatelengths of 0.5, 1.0, 1.5, and 2.0 µm and fan-out loadings of 1, 2, 4, and 8 (consisting of source-gate capacitances). All these test circuits are incorporated into a 6-mm by 6-mm master field. Sufficiently large slices to result in a 4 × 4 array of the master field are used. Si <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> implantation into <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\langle100\rangle</tex> Cr-doped Bridgman and not intentionally doped liquid encapsulated Czochralski (LEC) substrates have been used with success in terms of reproducibility, long range uniformity, and mobility. Since circuit yields are high, each slice provides a sufficiently large data base for a meaningful statistical analysis to be carried out for each circuit type. These data (propagation delay versus circuit type) together with power dissipation results are presented. Preliminary modeling results of the experimental data are also presented.

GaAs MESFET's by molecular beam epitaxy

The noise performance of T shaped Ti/W/Au gate GaAs Schottky-barrier field-effect transistors fabricated on channel layers grown by molecular-beam epitaxy (MBE) is reported. The nominal gate length was about 0.7 µm with a total gate width of 250 µm. Typical noise figure and the associated gain were 1.2 and 14 dB at 4 GHz, and 1.9 and 8.5 dB at 12 GHz. To out knowledge these are the best results reported to date on devices fabricated using MBE-grown GaAs. These preliminary results show the promise of MBE for high-quality GaAs FET's.

Low-noise GaAs field-effect transistors prepared by molecular beam epitaxy

The noise performance of ’’T’’ shaped Ti/W/Au gate GaAs Schottky-barrier field-effect transistors (FET’s) fabricated on channel layers grown by molecular beam epitaxy (MBE) is reported. The nominal gate length was about 0.7 μm with a total gate width of 250 μm. Typical noise figures and the associated gains at room temperature were 1.2 and 14 dB at 4 GHz, and 1.9 and 8.5 dB at 12 GHz. To our knowledge, these are the best results reported to date by MBE. These preliminary results, while not reaching the state of the art, do show the promise of MBE for high-quality GaAs FET’s.

Low-noise GaAs FET's prepared by ion implantation

The rapidly improving performance of low-noise GaAs FET's can to a large extent be attributed to advances in the material preparation technology. Ion implantation directly into bulk-grown semi-insulating substrate material represents an optimum approach by providing excellent control and reproducibility over the doping parameters in the active layer. This paper will review development efforts carried out to capitalize on these inherent advantages and discuss the results obtained from transistors fabricated by this method. Device modeling has been used to investigate the effects of profile tailoring and has served as a guide for selecting implant species, doses, and energies. This effort has paralleled the development of the implantation technology, which has addressed the problems of selecting suitable substrate material, deposition of suitable capping material for the post-implantation anneal, the study of doping profiles, and the diffusion during the anneal. The advances made in these areas will be discussed along with the fabrication procedures for the low-noise FET's. Favorable doping profiles were obtained by using Se implants as evidenced by the small variation in the measured transconductance versus gate voltage. The excellent uniformity and reproducibility obtained in the active layer parameters have resulted in tightly distributed transconductances, pinchoff voltages, and S-parameters. Measured parameters from five wafers have given typical standard deviations of less than 10 percent of the mean value. Packaged transistors with a nominal gate length of 1 µm have yielded noise figures of 1.1 dB at 4 GHz with 12- dB associated gain, while 2.5-dB noise figures have been achieved at 15 GHz with 7-dB gain from transistors mounted on a low parasitic carrier. These improved RF results combined with a high level of reproducibility present ion implantation as a very attractive method for fabricating low-noise GaAs FET's.

Electron-beam fabrication of submicron gates for GaAs FET’s

High-performance GaAs FET’s with nominal gate lengths of 0.5, 0.75, and 1.0 μm have been fabricated with electron-beam-lithography techniques. A hybrid process was developed which only required e-beam definition of the critical gate level and was otherwise compatible with the fabrication process developed for conventional optically defined gates. The source–drain metallization mask was modified to include alignment marks for the gate level and the source–drain metallization was augmented to give marks after alloying with acceptable secondary electron contrast against the GaAs background: ±2000 Å registration was routinely achieved over the 80×80 mil2 field. A test pattern which could be examined optically with rapid turnaround to determine the proper exposures for the various gate lengths was employed. The pattern evaluation was confirmed by resist exposure studies in conjunction with SEM examination. Evaluation of the test pattern together with corrections for the GaAs substrate backscatter and proximity effect allowed control of the gate lengths to ±10% over the entire slice. The gates were tapered at the mesa edge to prevent constriction of the resist over the step. The resist used was polymethyl methacrylate (PMMA) with a nominal thickness of 7500 Å and the developed pattern served as the lift-off mask for 4000–5000 Å of aluminum gate metallization. The nominal slice size used for these runs was slightly greater than 1 cm2 (420×420 mil2) and up to 588 devices were patterned in a single pumpdown. The exposure time required per slice, including stage step and alignment, was six minutes. Both small signal and power GaAs FET’s have been fabricated with e-beam defined gates. Small signal devices with 0.75μm gate lengths had 2.0 dB minimum noise figures with 10 dB gain at 9 GHz. Power devices with 4800-μm total gate width and 1-μm gate length had up to 4.1 W output power at 8 GHz with 4 dB gain.