Low-noise GaAs FET's prepared by ion implantation

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The rapidly improving performance of low-noise GaAs FET's can to a large extent be attributed to advances in the material preparation technology. Ion implantation directly into bulk-grown semi-insulating substrate material represents an optimum approach by providing excellent control and reproducibility over the doping parameters in the active layer. This paper will review development efforts carried out to capitalize on these inherent advantages and discuss the results obtained from transistors fabricated by this method. Device modeling has been used to investigate the effects of profile tailoring and has served as a guide for selecting implant species, doses, and energies. This effort has paralleled the development of the implantation technology, which has addressed the problems of selecting suitable substrate material, deposition of suitable capping material for the post-implantation anneal, the study of doping profiles, and the diffusion during the anneal. The advances made in these areas will be discussed along with the fabrication procedures for the low-noise FET's. Favorable doping profiles were obtained by using Se implants as evidenced by the small variation in the measured transconductance versus gate voltage. The excellent uniformity and reproducibility obtained in the active layer parameters have resulted in tightly distributed transconductances, pinchoff voltages, and S-parameters. Measured parameters from five wafers have given typical standard deviations of less than 10 percent of the mean value. Packaged transistors with a nominal gate length of 1 µm have yielded noise figures of 1.1 dB at 4 GHz with 12- dB associated gain, while 2.5-dB noise figures have been achieved at 15 GHz with 7-dB gain from transistors mounted on a low parasitic carrier. These improved RF results combined with a high level of reproducibility present ion implantation as a very attractive method for fabricating low-noise GaAs FET's.