Nominal Gate Length Research Articles

Theoretical simulation of negative differential transconductance in lateral quantum well nMOS devices

We present a theoretical study of the negative differential transconductance (NDT) recently observed in the lateral-quantum-well Si n-channel field-effect transistors [J. Appl. Phys. 118, 124505 (2015)]. In these devices, p+ doping extensions are introduced at the source-channel and drain-channel junctions, thus creating two potential barriers that define the quantum well across whose quasi-bound states resonant/sequential tunneling may occur. Our study, based on the quantum transmitting boundary method, predicts the presence of a sharp NDT in devices with a nominal gate length of 10-to-20 nm at low temperatures (∼10 K). At higher temperatures, the NDT weakens and disappears altogether as a result of increasing thermionic emission over the p+ potential barriers. In larger devices (with a gate length of 30 nm or longer), the NDT cannot be observed because of the low transmission probability and small energetic spacing (smaller than kBT) of the quasi-bound states in the quantum well. We speculate that the inability of the model to predict the NDT observed in 40 nm gate-length devices may be due to an insufficiently accurate knowledge of the actual doping profiles. On the other hand, our study shows that NDT suitable for novel logic applications may be obtained at room temperature in devices of the current or near-future generation (sub-10 nm node), provided an optimal design can be found that minimizes the thermionic emission (requiring high p+ potential-barriers) and punch-through (that meets the opposite requirement of potential-barriers low enough to favor the tunneling current).

Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25 µm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; ∼124 mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 ± 13 mV/V), and a high ION/IOFF current ratio (∼1 × 109) under a relatively low voltage condition (VD = 0.3 V, VG = 5 V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.

Comparative Simulation Analysis of Process-Induced Variability in Nanoscale SOI and Bulk Trigate FinFETs

This paper presents a comprehensive simulation study of the process and statistical variability in 16-nm technology node bulk and silicon-on-insulator (SOI) fin field effect transistors (FinFETs). The devices are carefully designed to offer good manufacturability while meeting the performance requirements of the 16-nm technology. First, the sensitivity of the two types of FinFETs to process- induced channel length, fin-width, and fin-height variability is carefully investigated and compared based on the threshold voltage, OFF-current, and overdrive current sensitivity. Possible improvement of the SOI substrate design for reduction of the SOI FinFET sensitivity to fin-width variation is also discussed. The individual and combined impact of the relevant statistical variability sources including random discrete dopants (RDDs), fin-line edge roughness, gate-line edge roughness, and metal gate granularity are studied and compared for the nominal 25-nm gate length FinFET designs.

Channel Thickness Effect on High-Frequency Performance of Poly-Si Thin-Film Transistors

In this letter, we present the high-frequency performances of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a nominal gate length of 0.22 μm. Owing to the short gate length and adoption of salicide process, cutoff frequency (fT) of 17 GHz and maximum oscillation frequency of ~ 21 GHz are obtained. The result suggests that the poly-Si TFT technology is applicable to RF integrated circuits up to 2 GHz. In addition, we also investigate the effects of channel thickness on the high-frequency characteristics of poly-Si TFTs. We find that the variation of fT with channel thickness is mainly due to the change in transconductance.

Gate-All-Around Single-Crystal-Like Poly-Si Nanowire TFTs With a Steep-Subthreshold Slope

We investigate the characteristics of single-crystal-like (SCL) poly-Si nanowire (SCL poly-Si NW) thin-film-transistors with gate-all-around (GAA) structures. The GAA SCL poly-Si NWs are prepared by a modified sidewall spacer process utilizing an amorphous silicon ( α-Si) mesa structure. The combination of the high surface-to-volume ratio of the NW and a nominal gate length of 0.25 μm lead to clear improvement in electrical performance, including a steep subthreshold swing (90±15 mV/dec), a virtual absence of drain-induced barrier lowering (21±13 mV/V), and a very high ON/OFF current ratio ~ 7×107 (VD=1 V, VG=3 V).

10‐GHz 4.69‐W/mm InAlN/GaN HFET on sapphire substrate

AbstractA high‐performance InAlN/GaN heterojunction field effect transistor with a nominal gate length of 0.25 μm was fabricated on a sapphire substrate. Low defect density and low sheet resistance were obtained for the heterostructure under tests. The fabricated device exhibited a negligible current collapse, and remarkable RF characteristics, i.e. a maximum output power density of 4.69 W/mm at 10 GHz, a linear gain of 11.8 dB, and a peak power‐added efficiency of 48%, suggesting the extraordinary performances reachable by InAlN based technology. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

18-GHz 3.65-W/mm Enhancement-Mode AlGaN/GaN HFET Using Fluorine Plasma Ion Implantation

Enhancement-mode (E-mode) AlGaN/GaN heterojunction field effect transistors (HFETs) with a nominal gate length of 0.35 μm are fabricated on a SiC substrate by fluorine plasma ion implantation without the use of gate recess. The threshold voltage is measured to be +0.2 V by linear extrapolation from the transfer characteristics. The E-mode device exhibits a saturation drain current density of 735 mA/mm at a gate bias of 4 V, a peak transconductance of 269 mS/mm, a current-gain cutoff frequency ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> ) of 39 GHz, and a maximum oscillation frequency ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) of 91 GHz. At 18 GHz, the fabricated E-mode device exhibits a maximum output power density of 3.65 W/mm, a linear gain of 11.6 dB, and a peak power-added efficiency of 42%. This is the first report of the large-signal performance of AlGaN/GaN E-mode HFETs in the Ku-band.

Comparison of laser voltage probing and mapping results in oversized and minimum size devices of 120 nm and 65 nm technology

Laser voltage probing (LVP) provides signal levels from circuit nodes through the backside of integrated circuits. Previous investigations presented voltage sweeping and modulation mapping, based on CW (continuous wave) 1319 nm laser. In this paper, large device structures have been compared with results of measurements on sub-micron devices – having nominal gate lengths and widths – including a ring oscillator (RO). All signals were obtained with a spectrum analyzer, requiring no internal trigger signals from the circuitry. On ROs, frequency shifts due to the thermal stimulation effect could be determined. Furthermore, a new measurement scheme for sign measurements of LVP signals is introduced.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate–source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-κ gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on–off current ratio (Ion/Ioff). Based on the investigation of on-current (Ion), off-current (Ioff), Ion/Ioff, intrinsic delay (τ), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/σ) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on Ion, Ioff and τ is also investigated for optimized underlap devices.

Stochastic simulation studies of molecular resists for the 32 nm technology node

Experiments and simulations suggest that low-molecular-weight resist materials could result in low line-edge roughness (LER) which is a critical parameter for the forthcoming technology nodes. Two positive molecular resist architectures are modeled with a stochastic lithography simulator and their LER behavior is quantified. The corresponding LER values obtained are less than 1nm, suggesting that such materials are promising for the fabrication of devices even down to the 32nm node. Two-dimensional lattices with the molecular resist architectures are created and combined with the stochastic lithography simulator and a simple etching modeling algorithm, in order to test the transferred line-width roughness (LWR) on the gate region of the pMOS and nMOS transistors of an inverter cell designed with 40nm nominal gate length. The role of the molecular resist architecture on the final LWR of transistor gate is discussed.

N‐face high electron mobility transistors with a GaN‐spacer

AbstractN‐face AlGaN (cap)/GaN (channel)/AlGaN (barrier)/GaN (buffer) high electron mobility transistors (HEMTs) provide a simple solution for strong confinement of the two‐dimensional electron gas (2DEG) from the back since carriers are induced on top of the AlGaN barrier. To reduce the adverse effects of random alloy scattering from the AlGaN barrier, an N‐face GaN‐spacer HEMT was designed with an epi‐structure consisting of an AlGaN (cap)/GaN (channel)/AlN/GaN (spacer)/AlGaN (barrier)/GaN (buffer). The 2DEG is confined at the GaN (channel)/AlN interface, while the GaN‐spacer layer separates the 2DEG from the AlGaN barrier. The large polarization‐induced electric field of the AlN and its large conduction band discontinuity with GaN provide strong confinement for good pinch‐off and low output conductance under high electric fields. Up to 20% improvement in electron mobility was measured in these devices. The devices showed a current gain cut‐off frequency (ft) of 24 GHz and power gain cut‐off frequency (fmax) of 44 GHz for a nominal gate length of 0.7 μm. An output power density of 4.5 W/mm was measured at 4 GHz, with 34% power added efficiency and a gain of 10.3 dB at a drain bias of 40 V. (© 2007 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

On the SiO/sub 2/-based gate-dielectric scaling limit for low-standby power applications in the context of a 0.13 μm CMOS logic technology

This paper describes a leading-edge 0.13 /spl mu/m low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I/sub off/) and gate delay (T/sub d/) performance at operating voltages (V/sub cc/) of 1.5 V and 1.2 V, devices with 0.11 /spl mu/m nominal gate length (L/sub g-nom/) and various gate-oxide thicknesses (T/sub ox/) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 /spl Aring/ in order to keep acceptable off-state power consumption at V/sub cc/=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T/sub ox/=26 /spl Aring/) is targeted for V/sub cc/=1.5 V with worst case I/sub off/ <10 pA//spl mu/m and nominal gate delay 24 ps/gate. Another design, named LP1 (T/sub ox/=22 /spl Aring/) is targeted for V/sub cc/=1.2 V with worst case I/sub off/<20 pA//spl mu/m and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 /spl mu/A//spl mu/m nominal drive currents at V/sub cc/ for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 /spl mu/m/sup 2/ cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T/sub ox/=22 /spl Aring/) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125/spl deg/C and V/sub cc/=1.5 V.

An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

This letter introduces an analytical model to represent line-edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices. The model partitions a given device into small unit cells along its width, each unit cell assumes a constant gate length (i.e., cell's width is small compared to LER spatial frequency). An analytical model is used to represent saturated threshold voltage dependency on the unit cell's gate length. Using this technique, an efficient and accurate model for LER effects (through V/sub ts/ variations) on off-state leakage and drive current is proposed and experimentally validated using 193 and 248 nm lithography for devices with 80-nm nominal gate lengths. Assuming that the deviation from the ideal 0-LER case remains constant from generation to generation, the model predicts that 3 nm or less LER is required for 50-60-nm state-of-the-art devices in the 0.1-μm technology node. Based on data presented, we suggest that the LER requirement for this technology node is attainable with an alternated phase-shift type of patterning process.

RF-CMOS performance trends

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1/f noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.

Coulomb blockade in low-mobility nanometer size Si MOSFET’s

We investigate coherent transport in Si:MOSFETs with nominal gate lengths 50 to 100nm and various widths at very low temperature. Independent of the geometry, localized states appear when G=e^{2}/h and transport is dominated by resonant tunnelling through a single quantum dot formed by an impurity potential. We find that the typical size of the relevant impurity quantum dot is comparable to the channel length and that the periodicity of the observed Coulomb blockade oscillations is roughly inversely proportional to the channel length. The spectrum of resonances and the nonlinear I-V curves allow to measure the charging energy and the mean level energy spacing for electrons in the localized state. Furthermore, we find that in the dielectric regime, the variance var(lng) of the logarithmic conductance lng is proportional to its average value <lng> consistent with one-electron scaling models.

Radiation-enhanced short channel effects due to multi-dimensional influence from charge at trench isolation oxides

Radiation enhanced drain induced barrier lowering (DIBL) was experimentally observed and verified by 3D simulations for submicron devices with trench isolation oxides. Submicron MOSFETs with shallow trench isolation were exposed to total-ionizing-dose radiation. Prior to irradiation, the devices exhibited near-ideal current-voltage characteristics, with no significant short-channel effects for as-drawn gate lengths of 0.4 /spl mu/m. Following irradiation, the off-state leakage current increased significantly for total doses above about 650 krad(SiO/sub 2/). In addition, the irradiated devices exhibited DIBL that increased the drain current by 5-10/spl times/ for a gate length of 0.4 /spl mu/m (the nominal minimum gate length for this process) and much more for slightly shorter devices (0.35 /spl mu/m). The increase in the off-state leakage current and the accompanying DIBL are shown to be associated with a parasitic field-effect transistor that is present at the edge of the shallow trench. Three-dimensional simulations are used to illustrate the effect. Simulations show that trapped charge at the trench sidewalls enhances the DIBL by depleting the edges of the channel. Radiation-induced charge may decrease the effectiveness of short-channel engineering.

Measurement of Doppler gate length using signal re-injection

Signal re-injection provides a versatile way of assessing the performance of ultrasonic scanners. The technique was used to measure the Doppler gate length of Duplex ultrasonic scanners operating in the pulsed Doppler mode. Five scanners were assessed, each with two different gate lengths, and the nominal gate length was compared with that measured. For most scanners the nominal gate length was less than that measured, the difference (measured minus nominal) varying between -0.9 mm and +8.0 mm. However, incomplete knowledge of the scanner characteristics, in particular receiver focusing and automatic gain control of the audio signal, made the results difficult to interpret. The test equipment used a perspex block to provide a fixed delay between the emitted and re-injected ultrasonic pulse. A more accurate assessment would have required a re-injection system with a variable delay between the pulses.

Complementary transistor technology for use in optoelectronic integrated circuits

A new compound semiconductor complementary transistor technology is proposed and the constituent devices demonstrated in discrete form. The n-channel transistor exhibits a peak transconductance of 110 mS/mm, a drain current density of 240 mA/mm and a unity current gain frequency of 9.5 GHz for a nominal gate length of 1 μm. The p-channel transistor has a peak transconductance of 35 mS/mm and a drain current density of 65 mA/mm for an effective gate length of 1.1 μm. Compatibility of this technology with optical devices is shown by fabricating a laser from the same material. Threshold current densities as low as 950 A/cm2 and external efficiencies of 50% are obtained.

Parasitic transients induced by floating substrate effect and bipolar transistor on SOI technologies

In this paper, we are dealing with consequences of the existence of parasitic bipolar[1] and kink effect[2] on transients occuring in SOI digital circuits. The two effects described below have been studied on NMOS transistors on SOI technology. To facilitate the acquisition of the different transients, we have used large transistors (7000?m for the first, and 100 ?m for the second) with nominal gate length (1.4?m). To characterize the first effect, we have used NMOS transistors with body ties. These ties are realized with P+ implantation in the N+ source diffusions, one body tie per ten microns of channel width. The kink effect induced transients have been characterized on usual NMOS transistors without tie.

A self-aligned GaAs MESFET process with WSi gates for analog and digital applications

A GaAs MESFET fabrication process based on self-aligned WSi gates with gatelengths down to 0.5 μm is described. A buried p-layer is employed to suppress short-channel effects. The shallow FET channels are connected to the deeper implants of the ohmic source and drain contacts by means of an intermediate-dose “lightly-doped drain” (LDD) implant. Owing to a planarization concept which allows the use of a low-resistance Au overlayer on top of the high resistivity WSi gates, the process yields FETs with excellent high-frequency performance. This is proved by transit frequencies ƒ t exceeding 30 GHz, maximum frequencies of oscillation ƒ max of typically 100 GHz, and a noise figure NF min of 1.0 dB at 12 GHz (nominal gatelength 0.5 μm). FETs with three different threshold voltages are fabricated. All three types of transistors have transconductances of 300 mS/mm or above. This combination of properties makes the technology suitable for the realization of digital as well as microwave circuits.