Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Abstract

Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25 µm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; ∼124 mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 ± 13 mV/V), and a high ION/IOFF current ratio (∼1 × 109) under a relatively low voltage condition (VD = 0.3 V, VG = 5 V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.