NMOS Devices Research Articles

Bias and geometry dependence of total-ionizing-dose effects in SOI FinFETs

In this paper, a systematic research on the total-ionizing-dose (TID) effects of NMOS and PMOS silicon-on-insulator (SOI) FinFETs is performed experimentally. The bias and geometry dependence of TID effects are analysed. The experimental results show that the threshold voltage (Vth) shift occurs in SOI FinFETs after x-ray irradiation. After 1 Mrad(Si) irradiation, the maximum Vth shift is about 40 mV. The ‘worst case’ irradiation bias conditions for NMOS and PMOS are TG and ON states, respectively, which induces the largest Vth shift after irradiation. The 3D TCAD simulation is carried out to further analyse the bias dependence results. Simulation results highlight the difference in electric field distribution in the buried oxide under different bias configurations, which leads to different distribution of irradiation-induced trapped charges. Finally, clear geometry dependence is observed in the TID experiment. Both NMOS and PMOS devices with larger fin width and/or smaller gate length are more sensitive to TID irradiation. The results deepen the understanding of the TID effect of SOI FinFETs and provide important technical support for the radiation-hardened research of FinFET technology.

Intrinsic Voltage Gain of Stacked GAA Nanosheet MOSFETs Operating at High Temperatures

In the semiconductor industry, the scaling down of devices has always been the driver in order to improve circuit area efficiency and high current drive, leading to the triple gate FinFET, which is the newest technology for high performance applications. However, it is believed that these devices cannot reach the sub 7 nm nodes and the GAA nanowires MOSFETs has emerged as one of the most promising candidates for this technology node, as it presents high density of integration and higher electrostatic control between gate and channel (1-2).The studied devices are GAA silicon nanosheet MOSFETs, fabricated at Imec, Leuven – Belgium, with two stacked channels with the vertical distance between the sheets of 7.5 nm, an EOT of 0.9 nm, a width of 15 nm and a channel length varying from 200nm down to 28nm.The threshold voltage (VTH) as a function of temperature is presented in figure 1, in which it is possible to observe that, VTH is reduced (in absolute value) for both n- and pMOS as temperature increases due to the fermi potential reduction. The VTH variation rate for these devices shows to be better when compared to other technologies, presenting a variation around -0.64 mV/ºC for the p-type, and -0.4 mV/ºC for the n-type, while planar fully depleted SOI devices reach around -0.8 mV/ºC (3), junctionless FinFETs can achieve around -0.94 mV/ºC (4) and bulk nFinFETs present values around -0.67 mV/ºC for narrow fins and -0.92 mV/ºC for wide ones (5).It is possible to see that the subthreshold swing (SS) values (figure2) are very close to the theoretical limit for the MOS technology, except for 28nm channel length pMOS devices, indicating that pMOS is more susceptible to short channel effects (SCEs) than the nMOS counterpart.In figure 3, the Drain Induced Barrier Lowering (DIBL) degrades when the temperature increases. DIBL degradation for both n- and pMOS with temperature are very similar, showing a variation rate of 0.11 mV/V.ºC. It is also important to note that although DIBL is affected by the temperature, the obtained values (except for L=28nm) are very small reaching in the worst case 50mV/V at 200ºC.The transconductance (gmsat) and output conductance (gd) on saturation region of n-type and p-type, showed in figure 4, decreases with increased temperature mainly due to the carrier mobility degradation. Although the gd degradation for L=28nm occurs for both caused by the channel length modulation, the p-type device presents a higher degradation in all range of temperature due to the gate to channel electrostatic coupling as already observed in the SS behavior (figure 2).The intrinsic voltage gain (AV) does not change significantly with temperature due to the compensation between the gm degradation and gd improvement as shown in figure 4. Long p-channel devices present higher Av (gm/gd) than n-type GAA FETs due to the smaller values of gd which is not compensated by the gm degradation. However, for short devices the higher gd degradation results in smaller Av. As said before, AV is calculated considering gmsat and gd and both depend on the mobility, so it is possible to note that AV is barely affected by temperature. Other important highlight is the obtained AV values for the studied GAA MOSFETs that are very high considering other multiple gate MOSFET structures. Both nMOS and pMOS nanosheet devices, with channel length of 100 nm, reach around 42 dB and 50dB respectively, while for bulk FinFETs , junctionless SOI nanowires and W-gate SOI nanowires the values achieved are 34 dB (6), 37 dB (7) and 40 dB (8), respectively, for the same VGT and similar channel length.Even though the longest devices show better SCE immunity and higher AV values, the device with a channel length of 28 nm still shows a good performance. The GAA nanosheet achieves AV of 33 dB and 28 dB, for n and p-type, respectively, while triple gate SOI nanowires, with channel length of 40 nm, and W-gate SOI nanowires, with channel length of 20 nm, presents values around 27 dB (9) and 20 dB (10), respectively. Figure 1

Study on the Charge Collection Mechanism of Single Event Transient Effect for Nano N-Channel Metal Oxide Semiconductor Field Effect Transistor

Based on the mechanism of charge collection, drift and diffusion, the influence of incident position, drain bias and incident particle LET (Linear Energy Transfer) value on the charge collection of NMOS devices is analyzed. It is found that the strongest electric field in drain depletion region is at 70 nm, and the maximum transient current is 3.43 mA. Drain bias affects the electric field in drain region. The higher drain bias is, the greater the electric field is, and the transient current is the larger of the peak value is, and the change of drain bias does not affect the diffusion current part; the larger the LET is, the larger the set current is, and the transient current peak value and collection charge increase linearly with the increase of LET. In addition, for a single transistor, the influence of the reduction of gate length on the bipolar amplification is analyzed, which is discovered that the reduction of gate length results in the aggravation of the single event effect. Therefore, the simulation results provide valuable reference for research on irradiation reliability and application of strained integrated circuit of Si Nano-scale NMOSFET.

Effect of electron radiation on small-signal parameters of NMOS devices at mm-wave frequencies

The effect of electron radiation on the forward-active small-signal model parameters for 0.35 μm CMOS devices is reported. Four devices with different gate widths were exposed to electron radiation using a Strontium 90 (Sr 90) radiation source at dose rates of 200 kRad (Si)/hr up to a total radiation dose of 2.7 MRad. S-parameters were measured, and small-signal models extracted, both pre-irradiation and at regular dose intervals. Relationships between small-signal model parameters and total radiation dose d were derived and used to calculate small-signal parameters. The major model variations due to total ionizing dose exposure were increases in the gate resistance (Rg), gate drain capacitance (Cgd) and gate source capacitance (Cgs), with a reduction in transconductances (gm and gds). This results in S11 and S22 becoming more resistive as d is increased, with a decrease in the unilateral gain, fT and fmax. The application of the data in predictive modelling of radiation damage is demonstrated.

Minimum leakage current optimization on 22 nm SOI NMOS device with HfO2/WSix/Graphene gate structure using Taguchi method.

To acquire the optimal value of the performance parameter, a bilayer graphene with silicon on insulator (SOI) was enhanced and analyzed on 22 nm NMOS device. The device is made of Hafnium Dioxide (HfO2) as a high-k material whereas Tungsten Silicide (WSix) as a metal gate. The Silvaco software ATHENA and ATLAS modules were applied to simulate the fabrication process of virtual devices and to verify the device’s electrical properties accordingly. The Taguchi L9 orthogonal array method was then used to enhance the device process parameters minimum leakage current (ILEAK) according to the International Technology Roadmap Semiconductor (ITRS) specification of 100nA/μm maximum range. The result from smaller-the-better (STB) for ILEAK is then reviewed by the percentage affecting the process parameter. The simulation result shows that the halo tilting angle is the most dominant factor for ILEAK optimization process. The optimized results indicate excellent device performance with ILEAK = 9.29746 nA/µm which is far lower than the prediction.

Source/Drain Materials for Ge nMOS Devices: Phosphorus Activation in Epitaxial Si, Ge, Ge1−xSnx and SiyGe1−x−ySnx

This paper benchmarks various epitaxial growth schemes based on n-type group-IV materials as viable source/drain candidates for Ge nMOS devices. Si:P grown at low temperature on Ge, gives an active carrier concentration as high as 3.5 × 1020 cm−3 and a contact resistivity down to 7.5 × 10−9 Ω.cm2. However, Si:P growth is highly defective due to large lattice mismatch between Si and Ge. Within the material stacks assessed, one option for Ge nMOS source/drain stressors would be to stack Si:P, deposited at contact level, on top of a selectively grown n-SiyGe1−x−ySnx at source/drain level, in line with the concept of Si passivation of n-Ge surfaces to achieve low contact resistivities as reported in literature (Martens et al. 2011 Appl. Phys. Lett., 98, 013 504). The saturation in active carrier concentration with increasing P (or As)-doping is the major bottleneck in achieving low contact resistivities for as-grown Ge or SiyGe1−x−ySnx. We focus on understanding various dopant deactivation mechanisms in P-doped Ge and Ge1−xSnx alloys. First principles simulation results suggest that P deactivation in Ge and Ge1−xSnx can be explained both by P-clustering and donor-vacancy complexes. Positron annihilation spectroscopy analysis, suggests that dopant deactivation in P-doped Ge and Ge1−xSnx is primarily due to the formation of Pn-V and SnmPn-V clusters.

A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics

A new behavioral model of gate-grounded NMOS (ggNMOS) device is proposed for electrostatic discharge (ESD) simulation of snapback behavior. The concise snapback model is a solution for the lack of snapback characteristics of build-in SPICE models in high voltage conditions. Modeling analysis, verification of snapback behavior and transient response under ESD stress are shown in this work. The new snapback model is intuitive to be understood and useful for ESD designers who do not have extensive modeling experience and skills. All the parameters in the proposed model like triggering voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t1</sub> ), holding voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</sub> ) and on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) can be directly extracted by transmission line pulsing (TLP) test. Further, simulation of transient response to human body model (HBM) stress is performed and the predicted currents and voltages are verified by the relevant HBM test.

Characterization and Modeling of 0.18μm Bulk CMOS Technology at Sub-Kelvin Temperature

Previous cryogenic electronics studies are mostly at 77K and 4.2K. Cryogenic characterization of a 0.18μm standard bulk CMOS technology (operating voltages: 1.8V and 5V) is presented in this paper. Several NMOS and PMOS devices with different width to length ratios (W/L) were extensively tested and characterized under various bias conditions at sub-kelvin temperature. In addition to devices dc characteristics, the kink effect and current overshoot phenomenon are observed and discussed at sub-kelvin temperature. Especially, the current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of MOSFET devices (1.8V W/L = 10μm/10μm) at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, bandgap widening, and uniformly distributed traps in the bandgap do not change the qualitative behavior of the threshold voltage over temperature. Care should be taken because dopant freezeout results in a different physical definition of the threshold voltage. Using different definitions changes significantly the threshold current level. The proposed model is experimentally validated with measurements in large-area nMOS and pMOS devices of a commercial 28-nm bulk CMOS process down to 4.2 K. Our modeling results suggest that a pMOS-specific phenomenon in the gate stack is responsible for the non-saturating temperature behavior of the threshold voltage in pMOS devices.

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Cryogenic device models are essential for the reliable design of the cryo-CMOS electronic interface necessary to build future large-scale quantum computers. This paper reports the characterization of the drain-current mismatch of NMOS and PMOS devices fabricated in a commercial 40-nm bulk CMOS process over the temperature range from 4.2K to 300 K. By analysing the variability of device parameters over a wide range of device area and length, the validity of the Pelgrom area-scaling law is assessed for the threshold voltage, the current factor and the subthreshold swing. The Croon model is employed to model the drain-current mismatch in moderate to strong inversion, while the weak inversion region is modeled by taking the subthreshold slope variability into account. This results in the first model capable of predicting CMOS-device mismatch over all operating regions and in the whole temperature range from 300K down to 4.2K.

First- and Second-Order Piezoresistive Coefficients of CMOS FETs From Strong Into Weak Inversion

For many years, researchers have noted that the stress response of MOS transistors exhibits strong deviations from a pure mobility behavior as the devices exit strong inversion, but there has been no easily accessible stress model that sensor designers can use in the design of their devices. In this work, generalized piezoresistance coefficients are presented that provide continuous modeling of the stress dependencies of CMOS FETs from weak into strong inversion. The models presented here incorporate both standard mobility variations plus the additional impact of threshold voltage changes on the stress responses in all regions of operation. The theory predicts both first- and second-order longitudinal and traverse piezoresistive coefficients for PMOS and NMOS devices that are verified with experimental results. The threshold voltage variations represent common-mode terms, so orthogonal differential pairs of MOSFETs can still be utilized to directly measure the important mobility components of the overall stress response, and the impact of the threshold voltage terms on sensor circuits may be reduced with differential design.

In-situ heater for thermal assist recovery of MOS devices in 28 nm UTBB FD-SOI CMOS technology

Preliminary results are reported on an in-situ heater for thermal assist recovery of MOS transistor and is demonstrated in 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) Ultra-Thin Body and Buried oxide (UTBB) high-k metal gate CMOS technology. This approach consists in functionalizing the source of a MOS device. We demonstrate that it is possible to heat the device with the current flowing between two split source contacts. Electrical and temperature measurements of the structures were made at wafer level. Moreover, 3D TCAD electro-thermal simulations assess the concept. The thermal resistor calibration on source and gate are performed on low and high VT NMOS devices with thin and thick high-k metal gate oxide. We have successfully reproduced the I-V responses on several samples at wafer level by electrical sweep in the 100 ns range into the split source contacts. The local temperature change effect was measured from room temperature up to +300 K. Finally, this first study shows that the thermal recovery is efficient and opens the door on new innovative solutions and could be applied on other technology nodes.

Source/Drain Materials for Ge nMOS Devices

This paper benchmarks various epitaxial growth schemes based on n-type group-IV materials as viable source/drain (S/D) materials for Ge nMOS devices. At present, P-doped Si grown at low temperature on Ge, gives an active carrier concentration as high as 3.5 x 1020 cm-3, and a contact resistivity (ρc) down to 7.5 x 10-9 Ω.cm2 when combined with Ti as contact metal without any post-epi activation anneal. However, the low temperature growth is non-selective in nature and yields defective Si:P due to the large lattice mismatch between Si and Ge. Our study indicates that the best option for Ge nMOS S/D stressors would be to stack Si:P, deposited at contact level, on top of a selectively grown n-SiyGe1-x-ySnx S/D.

Negative bias temperature instability (NBTI) effects on p-Si/n-InGaAs hybrid CMOSFETs for digital applications

This paper reports, for the first time, the influence of pMOS-negative-bias-temperature-instability (pMOS-NBTI) on the logic performance degradation of a hybrid CMOS inverter, comprising Si pMOS and In0.70Ga0.30As nMOS device, followed by a three-stage-ring-oscillator. The logic performance of an inverter is investigated in terms of high noise margin (NMH), rise time (tr), delay (td), and that for oscillators with reference to frequency of oscillations (fosc). Obtained results show percentage degradation values of 15.38%, 42.90%, 34.09%, and 23.44% for NMH, tr, td, and fosc, respectively, for a stress time of 10 s. It is also found that the oscillation frequency of the ring oscillator degrades ~ 30% for the stress time of 10,000 s compared to without NBTI value.

Epitaxial n++-InGaAs ultra-shallow junctions for highly scaled n-MOS devices

High electron mobility III-V semiconductors like InGaAs are excellent candidates for sub-10 nm n-metal-oxide-semiconductor (nMOS) devices. One of the critical challenges in downscaling III-V devices is achieving low-resistance contacts by forming low-defect, ultra-shallow junctions <9 nm in depth, with n-type dopant concentrations above 1019 cm−3. In the current study, we combine time-of-flight secondary ion mass spectrometry (ToF-SIMS) depth profile analysis, atomic force microscopy (AFM) imaging, and high-resolution transmission electron microscopy (HR-TEM) to determine the optimal doping strategy for growing Si-doped n++-In0.25Ga0.75As ultra-shallow junctions by molecular beam epitaxy. We test three different approaches to doping: homogeneous co-deposition, single δ-layer (continuous) doping, and triple δ-layer (pulsed) doping. We demonstrate the formation of technologically suitable n++-In0.25Ga0.75As junctions 5–7 nm deep, grown under As-rich conditions with a single δ-layer at temperatures as low as 400 °C. These junctions have peak Si concentrations between 6 × 1019 and 1 × 1020 cm−3 and high crystal quality. The surface self-organizes into smooth ripples or mounds, up to a peak dopant concentration of ~2 × 1020 cm-3. Above this value, enhanced diffusion of Si and In due to a large population of Ga vacancies increases lattice strain in the semiconductor epilayer, triggering a transition from 2D growth to 3D growth and the formation of In0.85Ga0.15As clusters on the surface.

On-Chip Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator

Process variability is one of the major concerns in semiconductor manufacturing in advanced technology nodes. This paper explains an all-digital technique to estimate the impact of threshold voltage ( ${V}_{\text{th}}$ ) of NMOS device under test (NDUT) using a reconfigurable ring oscillator (RRO) which consists of a chain of threshold voltage measurement cell (TVMC). The difference of periods of RRO due to two voltage levels, i.e., ${V}_{\text {dd}}$ and ( ${V}_{\text {dd}}-{V}_{\text {th}}$ ) at the intermediate node provides information about the impact of threshold voltage of an NDUT. A lognormal model is developed to extract the threshold voltage information from the RRO period difference. The maximum difference in predicting the threshold voltage from the proposed model and through SPICE simulation is found to be less than 1.5%. Measured results from 26 test chips in 130-nm process show the feasibility of estimating the $ {V}_{\text {th}}$ variability from the proposed RRO test structure. The proposed test circuit with 300 samples of NDUT occupies a silicon area of ${280} \,\, {\times }\,\, {64}\,\, {\mu } \text {m}^{{2}}$ .

Radiation tolerance impact of trap density near the drain and source regions of a MOSFET

In this paper, different sized NMOS devices, with the drain and gate terminals connected to 1.8 V and other terminals connected to ground potential, were irradiated. The effects of irradiation were investigated on the devices with either proper configuration of the drain and source terminals or with them reversed. Differences between the measured results corresponding to each configuration are attributed to different trap concentrations on the drain and source sides of STI. This idea has been tested by TCAD simulations, as well, and similar results have been obtained.

Influence of optimization of control factors on threshold voltage of 18 nm HfO2/TiSi2 NMOS

&lt;span&gt;This paper presents the influence of control factors as the process in development of 18 nm gate length NMOS transistor. The threshold voltage (VTH) can be minimized by optimal the control factors. Five control factors were selected through experiments. They are Adjustment VTH Implantation, Compensation Implantation, Compensation Energy Implantation, Source/Drain Implantation and Halo Implantation. While the two noise factors were introduced which are Phosphor Silicate Glass (PSG) temperature and Boron Phosphor Silicate Glass (BPSG) temperature to complete the combination with five control factors in process of Taguchi method L27 orthogonal array. The purpose of this research is to find the best value of interaction between combination controls factors and noise factors to achieve the best point of threshold voltage. In CMOS design, the threshold voltage is the benchmarking of physical parameter for determining the functional of transistor. The Virtual Wafer Fabrication SILVACO software was used to fabricate the 18 nm NMOS device. Hafnium Oxide (HfO2) and Titanium dioxide (TiO2) were utilized as the high-K materials and the Titanium Silicide (TiSi2) was utilized as metal gate. The statistics data are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) of L27 orthogonal array are executed to minimize the variance of threshold voltage. The results show that the optimization and interaction method is achieved to perform the threshold voltage value with least variance is 0.3055 volts while the target value that is 0.302 ± 12.7% volts from value recommendation by the International Roadmap for Semiconductor prediction 2012.&lt;/span&gt;

P-Edge NMOSFET for Improving TID Tolerance

This letter proposes a novel device structure named P-edge nMOS, in which high P+ doped belts are placed at the edges of the N+ source and drain. This structure is immune to the radiation-induced edge effects, thus, is able to improve total ionizing dose tolerance with much less area cost than enclosed layout transistors. Furthermore, P-edge nMOS is fully compatible with standard commercial technologies and can be used as a technique of radiation hardened by design. In order to evaluate the radiation tolerance of the new structure, sample transistors fabricated by the SMIC 350-nm commercial CMOS process with shallow trench isolation have been irradiated up to total doses of 2 Mrad(Si). The experimental results show that the leakage current of the P-edge nMOS is four orders of magnitude smaller than the normal nMOS device and the threshold voltage variation of the P-edge nMOS is reduced by about 90% when the dose is up to 2 Mrad(Si). The proposed P-edge nMOS can be a competitive alternative device to be used in CMOS integrated circuits for space applications.

On the investigation of cascode power amplifiers for 5G applications

AbstractBiCMOS processes provide not only standard NMOS devices, but also high‐performance SiGe HBTs, facilitating simultaneous use of both NMOS and HBT. This article adopts the advantages of both HBT and NMOS to achieve a high‐gain, high‐power, and efficient power amplifier (PA). Through an analysis of cascode amplifiers implementing different combinations of HBT and NMOS, a high‐performance 28‐GHz BiCMOS PA, which combines both HBT and body‐floating NMOS strengths to achieve 15.7‐dB gain, 19.6‐dBm saturated output power (Psat), 17.5‐dBm output 1‐dB compression (OP1dB), and 28.8% maximum PAE, is proposed for 5G applications.