Abstract
A new behavioral model of gate-grounded NMOS (ggNMOS) device is proposed for electrostatic discharge (ESD) simulation of snapback behavior. The concise snapback model is a solution for the lack of snapback characteristics of build-in SPICE models in high voltage conditions. Modeling analysis, verification of snapback behavior and transient response under ESD stress are shown in this work. The new snapback model is intuitive to be understood and useful for ESD designers who do not have extensive modeling experience and skills. All the parameters in the proposed model like triggering voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t1</sub> ), holding voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</sub> ) and on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) can be directly extracted by transmission line pulsing (TLP) test. Further, simulation of transient response to human body model (HBM) stress is performed and the predicted currents and voltages are verified by the relevant HBM test.
Highlights
SNAPBACK phenomenon is a commonplace for protection devices like gate-grounded NMOS or silicon-controlled rectifier (SCR) under electrostatic discharge (ESD) stress [1]–[7]
The proposed model is intuitive to be understood for ESD designers and does not require extensive modeling experience and skills
The snapback model can be embedded into the simulation tools for system-level or component-level ESD simulation
Summary
SNAPBACK phenomenon is a commonplace for protection devices like gate-grounded NMOS (ggNMOS) or silicon-controlled rectifier (SCR) under electrostatic discharge (ESD) stress [1]–[7]. This Verilog-A model can directly define the key parameters of snapback devices through if-else statement It is straightforward without extra complex equations, modeling of turn-on delay time is not included in this method. A behavioral snapback model can be implemented by a revised piecewise-linear model in IBIS syntax [23] The structure of this model is concise which only includes a resistor and a voltage source, but a series of relatively complex equations based on transient relaxation method are needed to define the resistor and voltage source. Based on TLP test, these elements can directly represent parameters of triggering voltage (Vt1), holding voltage (Vh) and on-resistance (Ron) without complex equations These parameters are important in characterizing ESD snapback devices according to the requirements of ESD design window.
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