NMOS Circuits Research Articles

Enhancement-Mode Ambipolar Thin-Film Transistors and CMOS Logic Circuits using Bilayer Ga2O3/NiO Semiconductors.

Recent advancements in power electronics have been driven by Ga2O3-based ultrawide bandgap (UWBG) semiconductor devices, enabling efficient high-current switching. However, integrating Ga2O3 power devices with essential silicon CMOS logic circuits for advanced control poses fabrication challenges. Researchers have introduced Ga2O3-based NMOS and pseudo-CMOS circuits for integration, but these circuits may either consume more power or increase the design complexity. Hence, this article proposes Ga2O3-based CMOS realized using heterogeneous 3D-stacked bilayer ambipolar transistors. These ambipolar transistors consist of HfO2/NiO/Ga2O3/NiO/HfO2 heterostructures that are wrapped around by the Ti/Au gate electrode, resulting in record high electron and hole current on/off ratios of 109 and 107. The threshold voltage, subthreshold swing, and current density measured from 100 ambipolar devices (across 5 batches) are around -7.99 ± 0.92 V (p-channel) and 7.81 ± 0.81 V (n-channel), 0.59 ± 0.07 V/dec (p-channel) and 0.61 ± 0.06 V/dec (n-channel), and 0.99 ± 0.26 mA/mm (p-channel) and 58.23 ± 12.99 mA/mm (n-channel), respectively. All the 100 ambipolar devices showed decent long-term stability over a period of 200 days, exhibiting reliable electrical performance. The threshold voltage shift (ΔVTH) after negative bias stressing for a period of 3500 s is around 11.52 V (p-channel) and 10.21 V (n-channel), respectively. Notably, the n-channels exhibit ∼2 orders higher on/off ratio than the best Ga2O3 unipolar transistors at 300 °C. Moreover, the polarities of ambipolar transistors are reconfigurable into p- or n-MOS, which are integrated to demonstrate CMOS inverter, NOR, and NAND logic gates. The switching periods from "0" to "1" and from "1" to "0" of NOR are 0.12 and 0.17 μs, and those of NAND are 0.16 and 0.13 μs. This work lays the foundation of oxide-semiconductor-based CMOS for future integrated electronics.

Carbon nanotube-based photovoltaic receiver with open-circuit voltage larger than 10 V

Carbon nanotubes (CNTs) based monolithic optoelectronic integrated circuits (OEICs) have been demonstrated at subwavelength scale, in which all components, including cascading detector, “trion” emitter and electronic processing circuits are monolithically fabricated using CNTs via a CMOS-compatible doping-free technique. In particular, the cascading detector is scaled down to deep-subwavelength scale of λ/12 (λ = 1800 nm) and generates a record photovoltage of 10.35 V under incident power density of 5.78 W cm−2; enabling efficient switch of subsequent electronic processing circuits between on-state and off-state to realize active control of the on-chip CNT emission for amplification (NMOS circuits) or diminution (PMOS circuits). These findings pave a new way for single-material based OEICs to move toward smaller and more powerful in the post-Moore era.

Nanowire NMOS Logic Inverter Characterization.

This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.

Static NMOS circuits for crossbar architectures using silicon nano-wire technology

This study shows the design and analysis of static NMOS gates composed of silicon nano-wire surrounding gate pull-down NMOSFETs (SGFETs) and p-type pull-up resistors as the primary building blocks to form high density circuits. The device geometry and doping concentration of NMOS transistors and p-type resistors are varied until the lowest noise margin and standby power dissipation are obtained for an inverter. The optimum NMOS transistor and p-type resistor configurations are subsequently used to build various NOR-type static logic gates including a full adder to evaluate the transient performance, power consumption and layout area of each gate. A power-saving technique that replaces the p-type pull-up resistor with a p-type MESFET is also investigated for large-scale logic strings. Simulation results indicate that the worst-case rise and fall delays for a full adder are 130 ps and 90 ps at no capacitive load, and increase by 27.5 ps and 10 ps per fan-out, respectively. The worst-case power dissipation for the same circuit is 186.4 µW. The full adder circuit occupies approximately a 25 μm2 area if laid out conventionally and 36 µm2 if laid out on a crossbar platform. Compared to same feature size conventional CMOS technologies, silicon nano-wire technology offers simplicity in interconnect routing and reduction in the layout area for similar circuit performance.

RF CMOS Reliability

In this chapter the effects of hot carrier on the reliability of NMOS transistors are investigated. First, it is explained why the hot carrier issue can be important in RF CMOS circuits. Important mechanisms of hot carrier generation are reviewed and some of the techniques used in the measurement of hot carrier damages are explained. Next, results of measurement of DC hot carrier stress on the NMOS transistors are presented. The main focus here is the RF performance of the NMOS devices and circuits mode of them, but DC parameters of the device such as its I-V characteristics and threshold voltage are presented, as they directly affect the RF performance. Finally, using the measurements of hot carrier effects on single NMOS transistors, the effects of hot carriers on three parameters of a low noise amplifier, matching, power gain and stability, are predicted using circuit simulation.

RF CMOS RELIABILITY

In this chapter the effects of hot carrier on the reliability of NMOS transistors are investigated. First, it is explained why the hot carrier issue can be important in RF CMOS circuits. Important mechanisms of hot carrier generation are reviewed and some of the techniques used in the measurement of hot carrier damages are explained. Next, results of measurement of DC hot carrier stress on the NMOS transistors are presented. The main focus here is the RF performance of the NMOS devices and circuits mode of them, but DC parameters of the device such as its I-V characteristics and threshold voltage are presented, as they directly affect the RF performance. Finally, using the measurements of hot carrier effects on single NMOS transistors, the effects of hot carriers on three parameters of a low noise amplifier, matching, power gain and stability, are predicted using circuit simulation.

A vertical-cavity surface-emitting laser appliqued to a 0.8-μm NMOS driver

An optoelectronic integrated circuit (OEIC) composed of a vertical-cavity surface-emitting laser (VCSEL) appliqued to an NMOS drive circuit was fabricated to form an optical link from the CMOS chip. A custom NMOS circuit was designed and fabricated through the MOSIS foundry service in a standard 0.8-μm CMOS process. InGaAs quantum-well VCSELs were grown, fabricated and tested on an n-type GaAs substrate. Next, the VCSELs underwent a substrate removal technique and were appliqued to the NMOS circuitry. The OEIC was tested at the chip level and showed an electrical to optical conversion efficiency of 1.09 mW/V. Modulation results are also discussed.

Modeling for bridging faults in nMOS combinational circuits

A transistor level model that fully describes the logical behavior of a circuit in the presence of bridging faults is presented for the nMOS combinational circuits. The proposed model is suitable for the circuits having static enhancement/depletion (E/D) load. Thus, the model can be applied to circuits like pseudo nMOS and CMOS non-threshold-logic (NTL). The model employs a logic transistor function (LTF) to examine the behavior of such circuits. The LTF model developed earlier for stuck faults in nMOS circuits is extended for bridging faults. Algorithms that were developed for the stuck faults in pseudo nMOS combinational circuits can be applied to generate the test vectors for bridging faults.

Simulation of hot-carrier induced MOS circuit degradation for VLSI reliability analysis

A new integrated simulation tool is presented for estimating the hot-carrier induced degradation of nMOS transistor characteristics and circuit performance. This reliability simulation tool incorporates: (1) an accurate 1-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors; and (2) physical models for both fundamental device-degradation mechanisms (charge trapping and interface trap generation). Hot-carrier induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. A repetitive simulation scheme ensures accurate prediction of the circuit-level degradation process under dynamic operating conditions. The evolution of hot-carrier related damage in each device is automatically simulated at predetermined time intervals, instead of extrapolating the long-term degradation using only the initial simulation results. Thus, the gradual variation of dynamic stress conditions is accounted for during the long-term damage estimates. >

NMOS and CMOS polysilicon drive circuits for liquid crystal displays

A number of circuits that form the basic elements needed for integration of the drive circuits for active matrix LC displays have been investigated. The circuits have been fabricated using a low temperature polysilicon process and measurements have been made of the circuit performance. NMOS and CMOS circuits have been compared and while ratioed NMOS circuits have a poor performance in terms of speed and power, ratioless NMOS and CMOS circuit can both provide high-speed low-power operation.

Design of ternary nMOS circuits based on the theory of clipping voltage switches

The theory of clipping voltage switches suitable for ternary nMOS circuits is proposed, assuming that the switching states of the elements and signals in a circuit should be described separately by using switching variables and signal variables. Threshold comparison operations and voltage-clipping operation are introduced, which can reflect the working principle of nMOS circuits. Their relative properties and the expressions of the logic functions are discussed. Based on the theory some basic ternary nMOS circuits are designed and simulated. Simulation results using SPICE show that these circuits have correct logic functions and desirable DC and transient characteristics.

Modeling and simulation of hot-carrier-induced device degradation in MOS circuits

The physical models and an integrated simulation tool are presented for estimating the hot-carrier-induced degradation of nMOS transistor characteristics and circuit performance. The proposed reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors. The hot-carrier-induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. The physical degradation model includes both fundamental device degradation mechanisms, i.e., charge trapping and interface trap generation. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions. >

An integrated air-gap-capacitor pressure sensor and digital readout with sub-100 attofarad resolution

The fabrication and characterization of an integrated air-gap-capacitor pressure sensor are presented. The capacitor fabrication process uses standard IC processing to create NMOS circuits, and an added polysilicon layer to create poly-to-n/sup +/ capacitors with a 0.6- mu m-thick dielectric using deposited oxide. Subsequent processing is used to produce deformable, parallel-plate, air-gap capacitors on the front side alongside MOS circuits. Sensor chips are fabricated using 100- mu m*100- mu m, 100-fF air-gap capacitors with on-chip circuitry. The sensor chip is a part of a capacitive measurement system that uses a charge-redistribution sense technique to achieve very high capacitance resolution. The behavior of the pressure sensor chips was studied as a function of applied pressure in the 0-240-kPa (0-35-psi) range. Measurements indicate a sensitivity of 0.93 mV/kPa (6.40 mV/psi) with a deflection of 10 nm/kPa (70 nm/psi) at 0-69 kPa (0-10 psi). Standard deviations indicate a static pressure resolution of 0.54 kPa (0.078 psi), which translates to 30 attofarads at a sampling frequency of 11 kHz. >

A transistor fault model for nMOS combinational circuits

Abstract A new fault model that incorporates both logic and circuit level description is presented. The model, called Logic Transistor Function (LTF), is developed to represent nMOS combinational circuits. The LTF uncovers extensive information about the structure of the circuit, and is utilized to specify the output of the fault-free and faulty circuits with single or multiple transistor stuck faults. The LTF is effective in modelling the sequential behaviour of the faulty combinational nMOS circuit. A procedure that relies on the LTF model is introduced to detect classical and non-classical faults. The circuit is tested by first partitioning the nMOS circuit and then obtaining the primitive D-cubes of the faulty partition. A variant of the D-algorithm may be applied to accomplish detection. The procedure is systematic, thus making it attractive for programming.

Shorts in self-checking circuits

It has been noted by several authors that the classical stuck-at logical fault model might not be an appropriate representation of certain real failures occurring in integrated circuits. Shorts are an important class of such faults. This article gives a detailed analysis of the effects of shorts in self-checking circuits and proposes techniques for dealing with them. More precisely, we show that, unlike other faults such as stuck-at, stuck-on, and stuck-open—which produce only single errors in the place they occur—shorts can produce double errors on the two shorted lines. In particular, feedback shorts can produce double errors on the two shorted lines. The double error is unidirectional for some feedback shorts and non-unidirectional for some others. Furthermore, in some technologies (e.g., CMOS), non-feedback shorts can also produce double non-unidirectional errors. We also show that unlike stuck-at, stuck-on, and stuck-open faults, redundant shorts can destroy the SFS property. Then we propose several techniques for coping with these problems and we illustrate the results by circuit implementation examples. The present study is given for NMOS and CMOS circuits but we show that it is valid for any other technology.

The optimization of a DRAM CMOS row decoder circuit

AbstractThis paper discusses a CMOS row decoder, which is indispensable to a VLSI DRAM. The factors involved in operational delay are analyzed and an investigation is done in order to be able to realize high‐speed operation, while maintaining the feature of low power consumption. The following structure was decided upon in order to achieve highspeed operation: the NAND gate of the CMOS row decoder is shared by more than one of the subdecoders. The size of the MOS transistors (MOST) which make up the gate is increased. In the size‐ratio of the p‐ and n‐channel MOSTs in the CMOS inverter of the next stage, the p‐channel MOST is made larger than in the usual design. A problem which arises from the unbalanced CMOS inverter is pointed out, and the optimization of the pre‐charge signal of the decoder is discussed in order to deal with this problem.For comparison, the optimized decoder circuit and an NMOS decoder are built into a IM DRAM test device, and their performances are compared. As a result of this test, it was verified that the operating current of the proposed CMOS row decoder is roughly 8 mA smaller than that of the NMOS circuit. The operational delay is negligible. By adopting the optimal precharge signal, a decoder circuit with a wide operational margin is realized.

Fully scaled 0.5 μm MOS circuits by synchrotron radiation X-ray lithography: Devices fabrication and overlay evaluation

Functional NMOS and CMOS circuits with fully-scaled 0.5 μm ground rules have been fabricated using synchroton radiation X-ray lithography for all device levels. The exposures were done at the VUV storage ring of the National Synchrotron Light Source at Brookhaven National Laboratory using a mask/wafer aligner developed at IBM Research. The performance of the aligner on both test wafers and device wafers is discussed, with emphasis on overlay. Characteristics of the fabricated circuits are also presented.

Design of a language for IC mask verification and net extraction

The paper describes the design of a language (the Mask Verification Language, or MVL) to interface with a programmable mask analysis system to check technology rules and extract netlists in a low-cost computing environment. The system operates in batch mode, i.e. mask designs are presented to the system, which checks them and reports errors. If there are problems, the mask designer can re-enter the mask editor to correct them. Running on a single-user workstation, the development loop has been found to be very fast. Legal devices and the technology description are presented to the system in MVL. Each device description contains a descriptive part which controls how a device is recognised, and a procedural part which controls how it is verified and processed once it has been recognised. As the programmer has no control over the order in which the descriptive sections are processed, it is possible for the system to optimise the mask operations necessary to perform the design rule checks and extract the circuit. The system is in regular use in a research environment, where design rules are not as inviolate as in industry. It has been used to encode the rules for I2L, NMOS and CMOS circuits, and can extract parasitic estimates as well as topological circuits.

An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation

A delay model for multiple delay simulation for NMOS and CMOS logic circuits is proposed. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance, and the device configuration ratio, with the polynomial coefficients determined so as to best fit the SPICE simulation results for a given fabrication process. This approach can easily be extended to the case of multiple-input transitions. The simulation results show that the proposed modes can predict the delay times within 5% error and with a speedup of three orders of magnitude for several circuits tested as compared with the SPICE simulation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Physical faults in MOS circuits and their coverage by different fault models

MOS VLSI circuits are often tested by using the stuck-at fault model to generate and evaluate test sequences that are intended to distinguish faulty from fault-free circuits. However, MOS circuits exhibit a wide variety of failure modes and there is no guarantee that the model accurately reflects the ways in which they fail. The paper gives many examples of faults taken from faulty NMOS circuits and discusses their associated fault-effects on a typical NMOS structure. It describes a series of experiments in which test patterns derived using different fault models are used to test 529 NMOS multiplexers. 12% of the chips tested and identified as being fault-free by a test set derived using the stuck-at fault model were faulty. In addition, two functional-level test sequences made up of identical test vectors arranged in different order were used to test the multiplexers. One correctly identified all the faulty circuits; the other identified 9% of the faulty circuits as being fault-free. The paper concludes that the stuck-at model is inadequate for testing MOS circuits, because of its use of a gate-level representation of the circuit under test. A more accurate method for generating and evaluating MOS circuit test patterns is to work from the switchlevel representation of the circuit under test, testing for transistor stuck-on and stuck-open faults.