Physical faults in MOS circuits and their coverage by different fault models

Abstract

MOS VLSI circuits are often tested by using the stuck-at fault model to generate and evaluate test sequences that are intended to distinguish faulty from fault-free circuits. However, MOS circuits exhibit a wide variety of failure modes and there is no guarantee that the model accurately reflects the ways in which they fail. The paper gives many examples of faults taken from faulty NMOS circuits and discusses their associated fault-effects on a typical NMOS structure. It describes a series of experiments in which test patterns derived using different fault models are used to test 529 NMOS multiplexers. 12% of the chips tested and identified as being fault-free by a test set derived using the stuck-at fault model were faulty. In addition, two functional-level test sequences made up of identical test vectors arranged in different order were used to test the multiplexers. One correctly identified all the faulty circuits; the other identified 9% of the faulty circuits as being fault-free. The paper concludes that the stuck-at model is inadequate for testing MOS circuits, because of its use of a gate-level representation of the circuit under test. A more accurate method for generating and evaluating MOS circuit test patterns is to work from the switchlevel representation of the circuit under test, testing for transistor stuck-on and stuck-open faults.