A transistor fault model for nMOS combinational circuits

Abstract

Abstract A new fault model that incorporates both logic and circuit level description is presented. The model, called Logic Transistor Function (LTF), is developed to represent nMOS combinational circuits. The LTF uncovers extensive information about the structure of the circuit, and is utilized to specify the output of the fault-free and faulty circuits with single or multiple transistor stuck faults. The LTF is effective in modelling the sequential behaviour of the faulty combinational nMOS circuit. A procedure that relies on the LTF model is introduced to detect classical and non-classical faults. The circuit is tested by first partitioning the nMOS circuit and then obtaining the primitive D-cubes of the faulty partition. A variant of the D-algorithm may be applied to accomplish detection. The procedure is systematic, thus making it attractive for programming.