Testing for stuck faults in CMOS combinational circuits

Abstract

In the paper, a new transistor model is developed with which to examine the behaviour of static CMOS circuits using a logic transistor function (LTF). The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behaviour of the circuit can be obtained from the fault free LTF by using a systematic procedure. The model assumes the following logic values (0, 1, I, M), where I and M imply an indeterminate logical value and a memory element, respectively. Both classical stuck-at faults and nonclassical transistor stuck faults are considered. Single and multiple faults are analysed in the model.The paper introduces an algorithm that is based on a modified version of the Boolean difference technique to obtain the test vectors. Primitive D-cubes of the fault can also be extracted for a specified subcircuit. To generate tests for single or multiple faults, a variant of the D-algorithm may be used.